EPM9560RC240-15N vs EPM9560RC240-20N 对比

详细并排对比 EPM9560RC240-15N 出自 Altera 和 EPM9560RC240-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-15N EPM9560RC240-20N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $27.85 $0.00
Series MAX 9000 —
Family MAX 9000 (third-generation Multiple Array MatriX) —
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
Maximum User I/O Pins 216 216
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Internal Counter Frequency (fCNT) 145 MHz 144 MHz
Global Setup Time (tFSU) [DATA_NEEDED: tFSU for -15 grade] —
Clock-to-Output Time (tFCO) [DATA_NEEDED: tFCO for -15 grade] —
电源电压 5.0 V 5.0 V
Logic Family CMOS (EEPROM-based) —
Programmability In-system programmable (IEEE 1532/JTAG) —
Boundary-Scan Test JTAG (IEEE 1149.1) —
工作温度 0C to +70C (Commercial) 0 C to +70 C (commercial)
封装 RQFP-240 (240-pin Plastic Quad Flat Pack) 240-pin RQFP (PowerQuad Flat Pack)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance - older Altera RQFP part] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000 (EPM9560)
Logic Type — Complex Programmable Logic Device (CPLD)
Pin-to-Pin Propagation Delay (tPD1) — 20 ns
Flip-Flop Setup Time (tSU) — 3.0 ns
Configuration Technology — EEPROM (in-system programmable)
Speed Grade — -20 (20 ns)
Lead-Free Status — [DATA_NEEDED: lead-free status]

数据手册与资源

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