EPM9560RC304-15C vs EPM9560RC304-2 Comparación
Comparación detallada lado a lado de EPM9560RC304-15C por Altera y EPM9560RC304-2 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteIntel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-15C | EPM9560RC304-2 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $24,50 | $55,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD - Erasable PLD) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| Usable Gates | 12,000 | Approximately 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins (maximum) | 212 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Tensión de alimentación | 5.0 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Encapsulado | 304-pin RQFP | 304-pin RQFP (RC) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | Commercial (0C to +70C) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | — | [DATA_NEEDED: macrocell count] |
| User I/O Pins | — | 304 |
| Speed Grade | — | -2 |
| Core Supply Voltage | — | 5.0 V |
| I/O Supply Voltage | — | 5.0 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 (boundary-scan + ISP) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |