EPM9560RC304-2N vs EPM9560RC304C-3 Comparación
Comparación detallada lado a lado de EPM9560RC304-2N por Intel y EPM9560RC304C-3 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera
EPM9560RC304C-3 ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-2N | EPM9560RC304C-3 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $149,00 | $95,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| Encapsulado | RQFP/RBGA-class 304-pin plastic carrier (RC304) | RBGGA-304 (Ceramic Ball Grid Array) |
| Speed Grade | -2 (mid-band) | -3 (3 ns pin-to-pin, commercial) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD value in ns] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage Tolerance | 5.0 V (3.3 V with level shifting) | — |
| Programming Technology | EPROM/EEPROM, non-volatile | — |
| In-System Programming | IEEE 1149.1 JTAG | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown (legacy part, pre-RoHS era) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells (Logic Elements) | — | 560 |
| Recuento de pines | — | 304 |
| User I/O Pins | — | 212 |
| Tensión de alimentación | — | 5 V |
| Programmability | — | In-system, non-volatile EEPROM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Logic Blocks | — | Logic Array Blocks (LABs) with PIA interconnect |