EPM9560RC304-3 vs EPM9560RCRC304-15 Comparación
Comparación detallada lado a lado de EPM9560RC304-3 por Intel y EPM9560RCRC304-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC304-3 | EPM9560RCRC304-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,90 | $0,00 |
| Family | MAX 9000 (EPLD) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | 560 |
| Maximum Operating Frequency | 95 MHz (speed grade -3) | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Technology | UV-erasable CMOS EPROM | — |
| Encapsulado | 304-pin RQFP (Plastic Quad Flat Pack) | 304-pin RQFP (PowerQuad Flat Pack) |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Programming Interface | JTAG / 4-wire ISP (ByteBlaster compatible) | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | [DATA_NEEDED: LAB count] |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Speed Grade | -3 (fastest) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 9000 (EPM9560) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| Tensión de alimentación | — | 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |
| Lead Finish | — | [DATA_NEEDED: lead finish] |