EPM9560RI208-20N vs EPM9560TC208-20 Comparación
Comparación detallada lado a lado de EPM9560RI208-20N por Intel y EPM9560TC208-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-20N | EPM9560TC208-20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $60,00 |
| Device Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | 12000 |
| Macrocells | 560 | 560 |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Encapsulado | 208-pin RQFP | TQFP-208 (TC208) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | Industrial (-40C to +85C) | [DATA_NEEDED: commercial/industrial temperature grade] |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| User I/O | — | 149 |
| Propagation Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Pin/Package Code | — | TC208 (JEDEC S-PQFP-G208) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Technology | — | CMOS EEPROM |
| Core Supply Voltage | — | 5 V |
| I/O Supply Voltage (MultiVolt) | — | 3.3 V or 5 V |
| In-System Programming | — | Yes (IEEE Std 1149.1 JTAG) |
| Flip-Flops | — | 772 |