EPM9560WC208-15 vs EPM9560RC208-15C Comparación
Comparación detallada lado a lado de EPM9560WC208-15 por Altera y EPM9560RC208-15C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560WC208-15 | EPM9560RC208-15C |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $105,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EEPROM-based CPLD (EPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Propagation Delay (tPD) | 16.6 ns | 15 ns |
| Speed Grade | -15 | -15 (15 ns) |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Encapsulado | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP |
| Terminal Pitch | 0.50 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Estado RoHS | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 12,000 |
| User I/O Pins | — | 149 |
| Maximum Counter Frequency | — | 117.6 MHz |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Rango de temperatura de funcionamiento | — | 0C to +70C (commercial) |
| Logic Architecture | — | Multiple Array MatriX (MAX) third generation |