EPM9560WC208-20 vs EPM9560RC208-20N Comparación
Comparación detallada lado a lado de EPM9560WC208-20 por Altera y EPM9560RC208-20N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete
Comparación de especificaciones
| Parámetro | EPM9560WC208-20 | EPM9560RC208-20N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,80 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| User I/O Pins | 149 | 149 |
| Maximum Propagation Delay (tPD) | 23.6 ns | — |
| Encapsulado | PQFP-208 (RQFP/WQFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Process Technology | CMOS, EEPROM-based | — |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | — |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | Lead-free (N suffix) |
| Lead-Free | [DATA_NEEDED] | — |
| Sin halógenos | [DATA_NEEDED] | — |
| Nivel MSL | [DATA_NEEDED] | [DATA_NEEDED: MSL level] |
| Device Family | — | MAX 9000 (EPM9560) |
| Usable Gates | — | 12,000 |
| Propagation Delay (tPD) | — | 20 ns |
| Tensión de alimentación | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Logic Architecture | — | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Flip-Flops | — | 772 (per EPM9560 series data) |
| Speed Grade | — | -20 (20 ns) |