EPM9560WC208-20 vs EPM9560RC208-20N Comparaison
Comparaison détaillée côte à côte de EPM9560WC208-20 par Altera et EPM9560RC208-20N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete
Comparaison des spécifications
| Paramètre | EPM9560WC208-20 | EPM9560RC208-20N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $25,80 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| User I/O Pins | 149 | 149 |
| Maximum Propagation Delay (tPD) | 23.6 ns | — |
| Boîtier | PQFP-208 (RQFP/WQFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Process Technology | CMOS, EEPROM-based | — |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | — |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | — |
| Température de fonctionnement | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | [DATA_NEEDED: operating temperature range] |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | Lead-free (N suffix) |
| Lead-Free | [DATA_NEEDED] | — |
| Sans halogène | [DATA_NEEDED] | — |
| Niveau MSL | [DATA_NEEDED] | [DATA_NEEDED: MSL level] |
| Device Family | — | MAX 9000 (EPM9560) |
| Usable Gates | — | 12,000 |
| Propagation Delay (tPD) | — | 20 ns |
| Tension d'alimentation | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Logic Architecture | — | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Flip-Flops | — | 772 (per EPM9560 series data) |
| Speed Grade | — | -20 (20 ns) |