H5CG28AGBDX022 vs H5CG24AGBDX022N Comparación
Comparación detallada lado a lado de H5CG28AGBDX022 por SK hynix y H5CG24AGBDX022N por SK hynix. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | H5CG28AGBDX022 | H5CG24AGBDX022N |
|---|---|---|
| Marca | SK hynix | SK hynix |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1,00 | $0,00 |
| Manufacturer | SK hynix | SK hynix |
| Product Family | H5CG2 series (DDR5 SDRAM) | H5CG24 series DDR5 SDRAM |
| Tipo de memoria | DDR5 SDRAM | DDR5 SDRAM |
| Density | [DATA_NEEDED: verified density in Gb] | 16 Gbit (2 GB) |
| Organización de memoria | [DATA_NEEDED: verified organization] | [DATA_NEEDED: x8 or x16] |
| Speed Grade | [DATA_NEEDED: verified speed grade] | — |
| Supply Voltage (VDD) | 1.1 V (DDR5 class nominal) | — |
| Package Type | [DATA_NEEDED: verified package and ball count] | [DATA_NEEDED: FBGA package code and body size] |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| ECC | On-die ECC (DDR5 feature) | — |
| Burst Length | 16 / 32 (DDR5 feature) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: verified temperature range] | [DATA_NEEDED: operating temperature range] |
| Interfaz | DDR5 synchronous interface | — |
| Estado RoHS | [DATA_NEEDED: verified RoHS status] | unknown |
| Packing | [DATA_NEEDED: verified packing type] | — |
| Nivel MSL | [DATA_NEEDED: verified MSL] | [DATA_NEEDED: MSL level] |
| Velocidad de datos | — | [DATA_NEEDED: data rate / speed bin] |
| VDD Supply Voltage | — | [DATA_NEEDED: VDD value] |
| VDDQ Supply Voltage | — | [DATA_NEEDED: VDDQ value] |
| Latencia CAS | — | [DATA_NEEDED: CL value] |
| Bank Groups | — | [DATA_NEEDED: bank group count] |
| On-Die ECC | — | Yes (DDR5 generation feature) |
| Tipo de interfaz | — | SSTL / POD (DDR5 per JEDEC) |