H5CG28AGBDX022 vs H5CG24AGBDX022N Comparaison
Comparaison détaillée côte à côte de H5CG28AGBDX022 par SK hynix et H5CG24AGBDX022N par SK hynix. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | H5CG28AGBDX022 | H5CG24AGBDX022N |
|---|---|---|
| Marque | SK hynix | SK hynix |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1,00 | $0,00 |
| Manufacturer | SK hynix | SK hynix |
| Product Family | H5CG2 series (DDR5 SDRAM) | H5CG24 series DDR5 SDRAM |
| Type de mémoire | DDR5 SDRAM | DDR5 SDRAM |
| Density | [DATA_NEEDED: verified density in Gb] | 16 Gbit (2 GB) |
| Organisation de la mémoire | [DATA_NEEDED: verified organization] | [DATA_NEEDED: x8 or x16] |
| Speed Grade | [DATA_NEEDED: verified speed grade] | — |
| Supply Voltage (VDD) | 1.1 V (DDR5 class nominal) | — |
| Package Type | [DATA_NEEDED: verified package and ball count] | [DATA_NEEDED: FBGA package code and body size] |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| ECC | On-die ECC (DDR5 feature) | — |
| Burst Length | 16 / 32 (DDR5 feature) | — |
| Température de fonctionnement | [DATA_NEEDED: verified temperature range] | [DATA_NEEDED: operating temperature range] |
| Interface | DDR5 synchronous interface | — |
| Statut RoHS | [DATA_NEEDED: verified RoHS status] | unknown |
| Packing | [DATA_NEEDED: verified packing type] | — |
| Niveau MSL | [DATA_NEEDED: verified MSL] | [DATA_NEEDED: MSL level] |
| Débit de données | — | [DATA_NEEDED: data rate / speed bin] |
| VDD Supply Voltage | — | [DATA_NEEDED: VDD value] |
| VDDQ Supply Voltage | — | [DATA_NEEDED: VDDQ value] |
| Latence CAS | — | [DATA_NEEDED: CL value] |
| Bank Groups | — | [DATA_NEEDED: bank group count] |
| On-Die ECC | — | Yes (DDR5 generation feature) |
| Type d'interface | — | SSTL / POD (DDR5 per JEDEC) |