LC4064B-5T44C vs LC4064B-5T44I Comparación
Comparación detallada lado a lado de LC4064B-5T44C por Lattice Semiconductor y LC4064B-5T44I por Lattice Semiconductor. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Lattice Semiconductor
LC4064B-5T44C - 64-Macro 5ns ISP CPLD | Lattice Semiconductor
LC4064B-5T44C NrndLattice Semiconductor
LC4064B-5T44I - 64-Macrocell 5ns In-System CPLD | Lattice
LC4064B-5T44I ✓ ActivoComparación de especificaciones
| Parámetro | LC4064B-5T44C | LC4064B-5T44I |
|---|---|---|
| Marca | Lattice Semiconductor | Lattice Semiconductor |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Device Type | Complex programmable logic device (CPLD) | Complex programmable logic device (CPLD) |
| Series | ispMACH 4000B SuperFAST high-density PLD | — |
| Logic Macro Count | 64 macro cells | — |
| Speed Grade | 5 ns | 5 ns |
| Programming | In-system programmable | — |
| Supported Supply Levels | 3.3 V, 2.5 V, and 1.8 V | — |
| Encapsulado | 44-pin TQFP | 44-pin TQFP |
| Tipo de montaje | Surface mount | Surface mount |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Frecuencia de reloj máxima | [DATA_NEEDED: maximum clock frequency] | — |
| Internal Registers | [DATA_NEEDED: internal register count] | — |
| Configuration Memory Type | [DATA_NEEDED: configuration memory type] | — |
| Programmable I/O Standards | [DATA_NEEDED: programmable I/O standards] | — |
| Input Voltage Tolerance | [DATA_NEEDED: input voltage tolerance] | — |
| Output Drive Current | [DATA_NEEDED: output drive current] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification status] | — |
| Architecture | — | SuperFAST high-density PLD |
| Macrocell Count | — | 64 macrocells |
| Supported Supply Voltages | — | 3.3 V, 2.5 V and 1.8 V |
| Configuration Method | — | In-system programmable |
| Configuration Retention | — | Non-volatile |
| Terminal Count | — | 44 terminals |
| Package Shape | — | Square |
| Lead Style | — | Gull wing |
| Peak Reflow Time | — | 30 s maximum |
| I/O Standard | — | [DATA_NEEDED: supported I/O standards] |
| Maximum Operating Frequency | — | [DATA_NEEDED: maximum operating frequency] |
| Number of User I/O | — | [DATA_NEEDED: user I/O count] |
| RoHS Compliance | — | [DATA_NEEDED: RoHS compliance status] |