LC4064B-5T44C vs LC4064B-5T44I Comparaison
Comparaison détaillée côte à côte de LC4064B-5T44C par Lattice Semiconductor et LC4064B-5T44I par Lattice Semiconductor. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Lattice Semiconductor
LC4064B-5T44C - 64-Macro 5ns ISP CPLD | Lattice Semiconductor
LC4064B-5T44C NrndLattice Semiconductor
LC4064B-5T44I - 64-Macrocell 5ns In-System CPLD | Lattice
LC4064B-5T44I ✓ ActifComparaison des spécifications
| Paramètre | LC4064B-5T44C | LC4064B-5T44I |
|---|---|---|
| Marque | Lattice Semiconductor | Lattice Semiconductor |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Actif |
| Device Type | Complex programmable logic device (CPLD) | Complex programmable logic device (CPLD) |
| Series | ispMACH 4000B SuperFAST high-density PLD | — |
| Logic Macro Count | 64 macro cells | — |
| Speed Grade | 5 ns | 5 ns |
| Programming | In-system programmable | — |
| Supported Supply Levels | 3.3 V, 2.5 V, and 1.8 V | — |
| Boîtier | 44-pin TQFP | 44-pin TQFP |
| Type de montage | Surface mount | Surface mount |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Fréquence d'horloge maximale | [DATA_NEEDED: maximum clock frequency] | — |
| Internal Registers | [DATA_NEEDED: internal register count] | — |
| Configuration Memory Type | [DATA_NEEDED: configuration memory type] | — |
| Programmable I/O Standards | [DATA_NEEDED: programmable I/O standards] | — |
| Input Voltage Tolerance | [DATA_NEEDED: input voltage tolerance] | — |
| Output Drive Current | [DATA_NEEDED: output drive current] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification status] | — |
| Architecture | — | SuperFAST high-density PLD |
| Macrocell Count | — | 64 macrocells |
| Supported Supply Voltages | — | 3.3 V, 2.5 V and 1.8 V |
| Configuration Method | — | In-system programmable |
| Configuration Retention | — | Non-volatile |
| Terminal Count | — | 44 terminals |
| Package Shape | — | Square |
| Lead Style | — | Gull wing |
| Peak Reflow Time | — | 30 s maximum |
| I/O Standard | — | [DATA_NEEDED: supported I/O standards] |
| Maximum Operating Frequency | — | [DATA_NEEDED: maximum operating frequency] |
| Number of User I/O | — | [DATA_NEEDED: user I/O count] |
| RoHS Compliance | — | [DATA_NEEDED: RoHS compliance status] |