LFE2-6E-5F256C vs LFE2-20E-5F484C Comparación
Comparación detallada lado a lado de LFE2-6E-5F256C por Lattice Semiconductor y LFE2-20E-5F484C por Lattice Semiconductor. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Lattice Semiconductor
LFE2-6E-5F256C - 6K Lattice ECP2 FPGA, 190 I/O | Lattice
LFE2-6E-5F256C Unknown
Comparación de especificaciones
| Parámetro | LFE2-6E-5F256C | LFE2-20E-5F484C |
|---|---|---|
| Marca | Lattice Semiconductor | Lattice Semiconductor |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Unknown | Unknown |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $0,00 |
| Device Type | ECP2 Field Programmable Gate Array (FPGA) | ECP2 Field Programmable Gate Array (FPGA) |
| Logic Elements | 6,000 cells | — |
| Logic Array Blocks | 750 LABs | — |
| User I/O | 190 pins | — |
| Total RAM | 56,320 bits | — |
| Tensión de alimentación | 1.14 V to 1.26 V | — |
| Nominal Supply Class | 1.2 V | — |
| Temperatura de unión de funcionamiento | 0°C to 85°C | — |
| Process Technology | 90 nm | — |
| Encapsulado | 256-pin FBGA, 17 x 17 mm | 484-BBGA |
| Package Type | FBGA | BGA |
| Number of Package Pins | 256 pins | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| DSP Capability | Advanced DSP blocks | DSP |
| SERDES Capability | [DATA_NEEDED: LFE2-6E-5F256C-specific SERDES capability] | — |
| Programming Configuration | [DATA_NEEDED: configuration memory and programming interface] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| Logic Cell Density | — | 21K LUTs |
| Input/Output Count | — | 331 I/O |
| Core Supply Voltage | — | 1.2 V |
| Speed Grade | — | -5 |
| Terminal Count | — | 484 balls |
| Programmable Device | — | Yes |
| FPGA Family | — | LatticeECP2 |
| Logic Technology | — | 90 nm CMOS |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| Frecuencia de reloj máxima | — | [DATA_NEEDED: maximum clock frequency] |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |