LS1021AXE7HNB557 vs LS1021AXE7HNB Comparación
Comparación detallada lado a lado de LS1021AXE7HNB557 por NXP Semiconductors y LS1021AXE7HNB por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
LS1021AXE7HNB557 - QorIQ LS1021A 800MHz Dual Cortex-A7 MPU | NXP
LS1021AXE7HNB557 ✓ ActivoComparación de especificaciones
| Parámetro | LS1021AXE7HNB557 | LS1021AXE7HNB |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,20 | $40,05 |
| Core Architecture | ARM Cortex-A7 (dual-core), 32-bit | ARM Cortex-A7 (dual-core) |
| Maximum Core Frequency | 800 MHz | — |
| L1 Cache (per core) | [DATA_NEEDED: 32 KB I-cache + 32 KB D-cache per datasheet family] | — |
| L2 Cache (shared) | [DATA_NEEDED: 512 KB shared L2 per LS1 family docs] | — |
| Memory Controller | DDR3L / DDR4 with ECC, up to 16-bit | — |
| Display Controller | LCDC + 2D-ACE graphics accelerator | — |
| Ethernet | 3x vTSEC Gigabit Ethernet MACs | 2x 10/100/1000 MAC (vTSEC, TSN-ready) |
| USB | USB 3.0 + USB 2.0 with PHY | 1x USB 3.0 + 1x USB 2.0 (with PHY) |
| SATA | SATA 3.0 (1x port) | 2x SATA 3.0 (6 Gbps) |
| PCIe | PCIe Gen 2.0 root complex + endpoint | 3x PCIe 2.0 controllers |
| CAN | 2x CAN-FD controllers | — |
| Security Engine | SEC (AES, 3DES, SHA, RSA, ECC) | — |
| Temperatura de funcionamiento | -40C to +105C (industrial) | — |
| Encapsulado | 525-FCPBGA, 19x19 mm, 0.8 mm pitch | 525-FCPBGA (19x19 mm) |
| Series | QorIQ Layerscape LS1 | — |
| Estado RoHS | Compliant | Compliant |
| Maximum CPU Frequency | — | 800 MHz |
| Rango de temperatura de funcionamiento | — | -40 C to +105 C (industrial) |
| Memory Interface | — | DDR3L / DDR4 with ECC, up to 1600 MT/s |
| Cache (per core) | — | 32 KB I-cache + 32 KB D-cache |
| LCDC | — | Integrated, up to 1920x1080 |
| Cryptographic Offload | — | SEC 5.x (IPSec/SSL/TLS/DTLS acceleration) |
| Other Interfaces | — | CAN, uQE, I2C, SPI, UART, QSPI, SD/MMC |
| Silicon Revision | — | Rev 2.0 |
| Tipo de montaje | — | Surface Mount (FCPBGA) |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |