LTC2256CUJ-14 vs LTC2150CUJ-14 Comparación
Comparación detallada lado a lado de LTC2256CUJ-14 por Analog Devices y LTC2150CUJ-14 por Analog Devices. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ ActivoComparación de especificaciones
| Parámetro | LTC2256CUJ-14 | LTC2150CUJ-14 |
|---|---|---|
| Marca | Analog Devices | Analog Devices |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,90 | $41,58 |
| Resolución | 14 bit | 14 bit |
| Sample Rate | 25 Msps | 170 Msps |
| Number of Inputs | 1 | — |
| Architecture | Pipelined | Pipelined |
| Tensión de alimentación | 1.8 V (single) | — |
| Power Dissipation | 35 mW at 25 Msps | — |
| INL | ±1 LSB (typical) | — |
| DNL | ±0.3 LSB (typical) | — |
| Transition Noise | 1.13 LSB RMS | 1.82 LSBRMS |
| SNR | 73 dB | — |
| Input Bandwidth (Full Power) | 800 MHz | — |
| Input Range | 1 Vp-p to 2 Vp-p (selectable, differential) | — |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS (selectable) | — |
| Output Supply Range (CMOS) | 1.2 V to 1.8 V | — |
| Encapsulado | 40-QFN (6 mm x 6 mm) | 40-QFN (6 mm × 6 mm) with exposed pad |
| Pin/Package Code | UJ (QFN-40, 6x6 mm) | — |
| Configuration Interface | Serial SPI port | Serial SPI port |
| Power-Saving Modes | Nap mode, full shutdown | Sleep and Nap modes |
| Optional Features | Clock duty-cycle stabilizer, data output randomizer | — |
| Temperatura de funcionamiento | 0C to +70C (commercial C-grade) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant (PBF suffix) | Compliant (Pb-free #PBF suffix) |
| Number of Channels | — | 1 |
| Analog Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| INL (typical) | — | ±0.85 LSB |
| DNL (typical) | — | ±0.25 LSB |
| Missing Codes | — | None over temperature |
| Full-Power Sample/Hold Bandwidth | — | 1.25 GHz |
| Digital Output Interface | — | DDR LVDS |
| Encode Clock Inputs | — | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) |
| Clock Duty-Cycle Stabilizer | — | Optional (selectable) |
| Latency | — | 5 clock cycles |