MC8640DTVJ1250HE vs MC8641DVU1000GE Comparación
Comparación detallada lado a lado de MC8640DTVJ1250HE por NXP Semiconductors y MC8641DVU1000GE por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
MC8640DTVJ1250HE - Dual-Core 1.25GHz PowerPC e600 SoC | NXP
MC8640DTVJ1250HE ✗ Fin de vidaNXP Semiconductors
MC8641DVU1000GE - Dual 1GHz e600 SoC, 1023-FCBGA | NXP
MC8641DVU1000GE ⚠ Última compraComparación de especificaciones
| Parámetro | MC8640DTVJ1250HE | MC8641DVU1000GE |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Fin de vida | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $439,13 | $295,50 |
| Core Architecture | PowerPC e600 | Power Architecture, superscalar, 7-stage pipeline |
| Number of Cores | 2 | — |
| Core Frequency | 1.25 GHz (per core, 2 x 1.25 GHz) | 1.0 GHz |
| Ancho del bus de datos | 32-bit | — |
| Temperatura de funcionamiento | -40C to +105C (industrial) | 0 C to +105 C |
| Memory Controller | DDR1/DDR2 with ECC | DDR1 / DDR2 with ECC |
| SIMD Engine | AltiVec | AltiVec (128-bit vector unit) |
| Ethernet | Gigabit Ethernet (multi-port) | 4 x 10/100/1000 Mbps MAC |
| PCI Express | Yes (integrated controllers) | 2 x PCIe interfaces |
| Serial RapidIO | Yes (integrated) | 2 x SRIO ports |
| Encapsulado | 1023-ball FCCBGA (33x33 mm) | 1023-ball FCCBGA (33 x 33 mm) |
| Tipo de montaje | Surface Mount | — |
| Silicon Revision | Rev 3 | Rev 3.0 |
| Estado RoHS | [DATA_NEEDED: RoHS compliance per specific lot] | — |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Processor Type | — | PowerPC e600 MPC86xx 32-Bit |
| Core Count | — | 2 (dual-core) |
| Maximum Core Frequency | — | Up to 1.5 GHz (family max) |
| Core Supply Voltage | — | 1.05 V |
| L1 Cache | — | 32 KB instruction + 32 KB data per core |
| L2 Cache | — | 1 MB unified backside |