P5010NXE1QMB557 vs P5010NXE1QMB Comparación
Comparación detallada lado a lado de P5010NXE1QMB557 por NXP Semiconductors y P5010NXE1QMB por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
P5010NXE1QMB557 - QorIQ P5010 e5500 SoC 1.6GHz FC-PBGA-1295 | NXP
P5010NXE1QMB557 ✓ ActivoNXP Semiconductors
P5010NXE1QMB - QorIQ P5 1.6GHz e5500 SoC | NXP | Networking
P5010NXE1QMB ✓ ActivoComparación de especificaciones
| Parámetro | P5010NXE1QMB557 | P5010NXE1QMB |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $205,00 | $195,50 |
| Family | QorIQ P5 | QorIQ P5 |
| Core Architecture | Power Architecture e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 1.6 GHz (1600 MHz) | — |
| Secondary Core Frequency | 1.2 GHz (1200 MHz, r2.0) | — |
| L1 I-Cache per Core | 32 KB | — |
| L1 D-Cache per Core | 32 KB | — |
| Memory Controller | DDR3/DDR3L with ECC | DDR3 / DDR3L with ECC up to 1.33 GT/s |
| PCIe Lanes | Yes | — |
| Serial RapidIO (SRIO) | Yes | — |
| Gigabit Ethernet | Yes (multiple SerDes lanes) | — |
| Security Engine (SEC) | Integrated | — |
| Hardware Acceleration | Integrated | — |
| Temperatura de funcionamiento | -40C to +105C (extended) | -40C to +105C (extended, NX suffix) |
| Encapsulado | 1295-ball FC-PBGA (37.5x37.5 mm) | 1295-FCPBGA, 37.5x37.5 mm, 1.00 mm pitch |
| Ball Pitch | 1.00 mm | — |
| Tipo de montaje | Surface Mount | — |
| Boundary Scan | Yes (IEEE 1149.1/JTAG) | — |
| Architecture | — | Power Architecture e5500, 64-bit |
| Core Count | — | 1 (single core) |
| CPU Frequency (nominal) | — | 1.6 GHz |
| CPU Frequency (turbo) | — | 2.0 GHz |
| L2 Cache | — | 512 KB per core |
| Ethernet | — | Gigabit Ethernet (multiple MACs) |
| PCIe | — | PCI Express Gen2 (multiple lanes) |
| Serial RapidIO | — | 2x SRIO ports |
| Security Engine | — | SEC 4.x (E1 suffix enabled) |
| HW Acceleration | — | Pattern matching engine for packet classification |
| Core Voltage | — | 1.1 V |
| Process | — | 45 nm CMOS |
| Estado RoHS | — | Compliant |