RTAX2000S-1CGS624EV vs RTAX2000SL-1CGS624B Comparación
Comparación detallada lado a lado de RTAX2000S-1CGS624EV por Microchip Technology y RTAX2000SL-1CGS624B por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ ActivoMicrochip Technology
RTAX2000SL-1CGS624B - Rad-Tolerant FPGA 2M Gates CCGA624 | Microchip
RTAX2000SL-1CGS624B ✓ ActivoComparación de especificaciones
| Parámetro | RTAX2000S-1CGS624EV | RTAX2000SL-1CGS624B |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3.600,00 | $0,00 |
| System Gates | 2,000,000 | — |
| Logic Cells (CLBs) | 21504 | — |
| Total Cells | 32256 | — |
| Additional ASIC Equivalent Gates | 250000 | — |
| Encapsulado | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) | 624-pin Ceramic Column Grid Array (CCGA / CGA-624, ceramic) |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) | 1.5 V |
| Temperatura de funcionamiento | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Maximum Frequency | 649 MHz | — |
| Logic Family | CMOS | — |
| SEU Immunity | SEU-hardened registers, immune to single-event upsets to specified LET threshold | — |
| SEU Rate | < 10-10 errors/bit-day | — |
| Configuration | One-time programmable anti-fuse, live at power-up, single chip | Live at power-up, single-chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Tipo de montaje | Surface Mount | Surface Mount |
| Product Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | — |
| Thermal Resistance Basis | JEDEC JESD51 simulation conditions (per datasheet) | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O bank voltage] | — |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | RTAX-S/SL Radiation-Tolerant FPGA |
| Logic Blocks (CLBs) | — | 21504 |
| Equivalent System Gates | — | 2000000 |
| ASIC Gates | — | 250000 |
| Speed Grade | — | -1 |
| Frecuencia de reloj máxima | — | 649 MHz (family max, Jotrin listing) |
| Programmability | — | One-Time Programmable (antifuse) |
| Radiation Tolerance | — | Radiation-tolerant (space-flight qualified family) |
| I/O Count | — | [DATA_NEEDED: user I/O count] |