RTAX2000S-1CGS624EV vs RTAX2000SL-1CGS624B Comparaison
Comparaison détaillée côte à côte de RTAX2000S-1CGS624EV par Microchip Technology et RTAX2000SL-1CGS624B par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ ActifMicrochip Technology
RTAX2000SL-1CGS624B - Rad-Tolerant FPGA 2M Gates CCGA624 | Microchip
RTAX2000SL-1CGS624B ✓ ActifComparaison des spécifications
| Paramètre | RTAX2000S-1CGS624EV | RTAX2000SL-1CGS624B |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3 600,00 | $0,00 |
| System Gates | 2,000,000 | — |
| Logic Cells (CLBs) | 21504 | — |
| Total Cells | 32256 | — |
| Additional ASIC Equivalent Gates | 250000 | — |
| Boîtier | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) | 624-pin Ceramic Column Grid Array (CCGA / CGA-624, ceramic) |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) | 1.5 V |
| Température de fonctionnement | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Maximum Frequency | 649 MHz | — |
| Logic Family | CMOS | — |
| SEU Immunity | SEU-hardened registers, immune to single-event upsets to specified LET threshold | — |
| SEU Rate | < 10-10 errors/bit-day | — |
| Configuration | One-time programmable anti-fuse, live at power-up, single chip | Live at power-up, single-chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Type de montage | Surface Mount | Surface Mount |
| Product Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | — |
| Thermal Resistance Basis | JEDEC JESD51 simulation conditions (per datasheet) | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O bank voltage] | — |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | RTAX-S/SL Radiation-Tolerant FPGA |
| Logic Blocks (CLBs) | — | 21504 |
| Equivalent System Gates | — | 2000000 |
| ASIC Gates | — | 250000 |
| Speed Grade | — | -1 |
| Fréquence d'horloge maximale | — | 649 MHz (family max, Jotrin listing) |
| Programmability | — | One-Time Programmable (antifuse) |
| Radiation Tolerance | — | Radiation-tolerant (space-flight qualified family) |
| I/O Count | — | [DATA_NEEDED: user I/O count] |