RTAX250S-CQ208PROTO vs RTAX250SL-1CQ208PROTO Comparación

Comparación detallada lado a lado de RTAX250S-CQ208PROTO por Microchip Technology y RTAX250SL-1CQ208PROTO por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Microchip Technology
RTAX250S-CQ208PROTO RTAX250S-CQ208PROTO - Rad-Tolerant FPGA 250kG CQ208 | Microchip

RTAX250S-CQ208PROTO - Rad-Tolerant FPGA 250kG CQ208 | Microchip

RTAX250S-CQ208PROTO ✓ Activo
Microchip Technology
RTAX250SL-1CQ208PROTO RTAX250SL-1CQ208PROTO - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-1CQ208PROTO - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-1CQ208PROTO ✓ Activo

Comparación de especificaciones

Parámetro RTAX250S-CQ208PROTO RTAX250SL-1CQ208PROTO
Marca Microchip Technology Microchip Technology
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Activo Activo
Estado del stock In Stock In Stock
Precio unitario (USD) $0,00 $0,00
Family RTAX-S/SL Radiation-Tolerant FPGAs RTAX-S/SL Radiation-Tolerant FPGAs
Equivalent System Gates 250,000 gates 250,000
ASIC Gates (module) 30,000 gates —
CLBs 2816 —
Logic Cells 4224 4224
Core Supply Voltage 1.425 V to 1.575 V (1.5 V nominal) —
Process Technology CMOS —
Configuration Technology Antifuse (one-time programmable) —
Encapsulado CQ208 (208-pin ceramic) CQFP-208 (CQ208) ceramic quad flat pack
Radiation Tolerance Radiation-tolerant (space-flight grade family) —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
Clocking Segmentable clocks, chip-wide highway routing —
Configuration State Live at power-up, single-chip form factor —
Prototyping Flow Libero SoC conversion to Axcelerator device (AC170) —
Supported Prototyping Adaptor Aldec ACT-H600-CQ208 —
Temperatura de funcionamiento [DATA_NEEDED: Operating Temperature Range] [DATA_NEEDED: operating temperature range]
Speed Grade Standard (non -1) per ordering code -1
Configurable Logic Blocks (CLBs) — 2816
Combinatorial CLB Delay — 0.93 ns maximum (minimum -1 speed grade per source data)
Technology — CMOS antifuse (one-time programmable)
Total Ionizing Dose Tolerance — Enhanced (SL variant)
Configuration — Live at power-up (antifuse, no boot device)
Clock Features — Segmentable chip-wide clocks
Tipo de montaje — Surface Mount
Application Grade — Space-flight (radiation-tolerant), PROTO screening
Tensión de alimentación — [DATA_NEEDED: core supply voltage]
Estado RoHS — [DATA_NEEDED: RoHS status]

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