RTAX250S-CQ208PROTO vs RTAX250SL-1CQ208PROTO Comparaison

Comparaison détaillée côte à côte de RTAX250S-CQ208PROTO par Microchip Technology et RTAX250SL-1CQ208PROTO par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.

Microchip Technology
RTAX250S-CQ208PROTO RTAX250S-CQ208PROTO - Rad-Tolerant FPGA 250kG CQ208 | Microchip

RTAX250S-CQ208PROTO - Rad-Tolerant FPGA 250kG CQ208 | Microchip

RTAX250S-CQ208PROTO ✓ Actif
Microchip Technology
RTAX250SL-1CQ208PROTO RTAX250SL-1CQ208PROTO - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-1CQ208PROTO - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-1CQ208PROTO ✓ Actif

Comparaison des spécifications

Paramètre RTAX250S-CQ208PROTO RTAX250SL-1CQ208PROTO
Marque Microchip Technology Microchip Technology
Catégorie FPGA & CPLD FPGA & CPLD
Statut du cycle de vie Actif Actif
Statut du stock In Stock In Stock
Prix unitaire (USD) $0,00 $0,00
Family RTAX-S/SL Radiation-Tolerant FPGAs RTAX-S/SL Radiation-Tolerant FPGAs
Equivalent System Gates 250,000 gates 250,000
ASIC Gates (module) 30,000 gates —
CLBs 2816 —
Logic Cells 4224 4224
Core Supply Voltage 1.425 V to 1.575 V (1.5 V nominal) —
Process Technology CMOS —
Configuration Technology Antifuse (one-time programmable) —
Boîtier CQ208 (208-pin ceramic) CQFP-208 (CQ208) ceramic quad flat pack
Radiation Tolerance Radiation-tolerant (space-flight grade family) —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
Clocking Segmentable clocks, chip-wide highway routing —
Configuration State Live at power-up, single-chip form factor —
Prototyping Flow Libero SoC conversion to Axcelerator device (AC170) —
Supported Prototyping Adaptor Aldec ACT-H600-CQ208 —
Température de fonctionnement [DATA_NEEDED: Operating Temperature Range] [DATA_NEEDED: operating temperature range]
Speed Grade Standard (non -1) per ordering code -1
Configurable Logic Blocks (CLBs) — 2816
Combinatorial CLB Delay — 0.93 ns maximum (minimum -1 speed grade per source data)
Technology — CMOS antifuse (one-time programmable)
Total Ionizing Dose Tolerance — Enhanced (SL variant)
Configuration — Live at power-up (antifuse, no boot device)
Clock Features — Segmentable chip-wide clocks
Type de montage — Surface Mount
Application Grade — Space-flight (radiation-tolerant), PROTO screening
Tension d'alimentation — [DATA_NEEDED: core supply voltage]
Statut RoHS — [DATA_NEEDED: RoHS status]

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