SI5341B-D13308-GM vs SI5345A-D06546-GM Comparación
Comparación detallada lado a lado de SI5341B-D13308-GM por Skyworks Solutions y SI5345A-D06546-GM por Silicon Labs. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Skyworks Solutions
SI5341B-D13308-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
SI5341B-D13308-GM ✓ ActivoSilicon Labs
SI5345A-D06546-GM - 10-Output Any-Freq Jitter Attenuator | Silicon Labs
SI5345A-D06546-GM ✓ ActivoComparación de especificaciones
| Parámetro | SI5341B-D13308-GM | SI5345A-D06546-GM |
|---|---|---|
| Marca | Skyworks Solutions | Silicon Labs |
| Categoría | Clock & Timing | Clock & Timing |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,55 | $14,20 |
| Función | Clock generator | Clock Multiplier / Jitter Attenuator |
| Número de salidas | 10 | 10 |
| Output Frequency Range | Up to 350 MHz (any-frequency) | — |
| Number of Reference Inputs | 4 | — |
| Phase Jitter (12 kHz to 20 MHz) | 0.09 ps RMS (typical) | — |
| Output Formats | LVDS, LVPECL, LVCMOS, HCSL (selectable) | — |
| Frequency Synthesis Modes | Integer and Fractional-N | — |
| Supply Voltage (Core) | 1.8 V / 3.3 V | — |
| Host Interface | I2C / SPI (configurable) | — |
| Configuration Memory | Internal EEPROM (autonomous power-up) | — |
| Encapsulado | 64-pin QFN with exposed pad (64-VFQFN-EP) | 64-pin QFN (10x10 mm) with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | -40C to +85C (industrial) | — |
| Nivel MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Estado RoHS | Compliant | Compliant |
| Max Output Frequency | — | 1028 MHz |
| Number of Inputs | — | 1 reference input pair (XA/XB) |
| Jitter (12 kHz to 20 MHz) | — | <200 fs RMS typical [DATA_NEEDED: exact figure] |
| Output Types Supported | — | LVPECL, LVDS, HCSL, CML, CMOS, SSTL (per-pin configurable) |
| Frequency Synthesis Range | — | 1 Hz to 1.028 GHz per output |
| Architecture | — | MultiSynth fractional-N DSPLL |
| Reference Input | — | Differential pair (XA/XB) |
| Core Supply Voltage | — | 1.8 V or 3.3 V (single rail) [DATA_NEEDED: nominal typical] |
| Control Interface | — | I2C / SPI (ClockBuilder Pro configurable) |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) [DATA_NEEDED: exact grade letter] |
| Lead Free | — | Yes |