SI5341B-D13308-GM vs SI5345A-D06546-GM Comparaison
Comparaison détaillée côte à côte de SI5341B-D13308-GM par Skyworks Solutions et SI5345A-D06546-GM par Silicon Labs. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Skyworks Solutions
SI5341B-D13308-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
SI5341B-D13308-GM ✓ ActifSilicon Labs
SI5345A-D06546-GM - 10-Output Any-Freq Jitter Attenuator | Silicon Labs
SI5345A-D06546-GM ✓ ActifComparaison des spécifications
| Paramètre | SI5341B-D13308-GM | SI5345A-D06546-GM |
|---|---|---|
| Marque | Skyworks Solutions | Silicon Labs |
| Catégorie | Clock & Timing | Clock & Timing |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,55 | $14,20 |
| Fonction | Clock generator | Clock Multiplier / Jitter Attenuator |
| Nombre de sorties | 10 | 10 |
| Output Frequency Range | Up to 350 MHz (any-frequency) | — |
| Number of Reference Inputs | 4 | — |
| Phase Jitter (12 kHz to 20 MHz) | 0.09 ps RMS (typical) | — |
| Output Formats | LVDS, LVPECL, LVCMOS, HCSL (selectable) | — |
| Frequency Synthesis Modes | Integer and Fractional-N | — |
| Supply Voltage (Core) | 1.8 V / 3.3 V | — |
| Host Interface | I2C / SPI (configurable) | — |
| Configuration Memory | Internal EEPROM (autonomous power-up) | — |
| Boîtier | 64-pin QFN with exposed pad (64-VFQFN-EP) | 64-pin QFN (10x10 mm) with exposed pad |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | -40C to +85C (industrial) | — |
| Niveau MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Statut RoHS | Compliant | Compliant |
| Max Output Frequency | — | 1028 MHz |
| Number of Inputs | — | 1 reference input pair (XA/XB) |
| Jitter (12 kHz to 20 MHz) | — | <200 fs RMS typical [DATA_NEEDED: exact figure] |
| Output Types Supported | — | LVPECL, LVDS, HCSL, CML, CMOS, SSTL (per-pin configurable) |
| Frequency Synthesis Range | — | 1 Hz to 1.028 GHz per output |
| Architecture | — | MultiSynth fractional-N DSPLL |
| Reference Input | — | Differential pair (XA/XB) |
| Core Supply Voltage | — | 1.8 V or 3.3 V (single rail) [DATA_NEEDED: nominal typical] |
| Control Interface | — | I2C / SPI (ClockBuilder Pro configurable) |
| Température de fonctionnement | — | -40C to +85C (industrial) [DATA_NEEDED: exact grade letter] |
| Lead Free | — | Yes |