THS1040CPWRG4 vs THS1215IPWR Comparación
Comparación detallada lado a lado de THS1040CPWRG4 por Texas Instruments y THS1215IPWR por Texas Instruments. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Texas Instruments
THS1040CPWRG4 - 10-Bit 40 MSPS Low-Power ADC | Texas Instruments
THS1040CPWRG4 ✓ ActivoTexas Instruments
THS1215IPWR - 12-Bit, 15 MSPS Low-Power ADC | Texas Instruments
THS1215IPWR ✓ ActivoComparación de especificaciones
| Parámetro | THS1040CPWRG4 | THS1215IPWR |
|---|---|---|
| Marca | Texas Instruments | Texas Instruments |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,10 | $6,72 |
| Resolución | 10 bit | 12 bit |
| Number of Channels | 1 Input | 1 |
| Frecuencia de muestreo | 40 MSPS | — |
| Architecture | Pipelined | Pipelined CMOS ADC |
| Analog Supply Voltage | 3 V | — |
| Digital Supply Voltage | 3 V | — |
| Analog Input Configuration | Single-ended or Differential | — |
| Differential Nonlinearity (DNL) | ±0.45 LSB (typ) | — |
| Signal-to-Noise Ratio (SNR) | 60 dB typ at 4.8 MHz | — |
| Spurious-Free Dynamic Range (SFDR) | 72 dB | — |
| Internal Voltage Reference | Adjustable, supports 1 Vp-p and 2 Vp-p full-scale | — |
| Input Range | 1 Vp-p to 2 Vp-p (configurable) | — |
| Rango de temperatura de funcionamiento | 0C to +70C (commercial grade) | — |
| Encapsulado | 28-pin TSSOP (PW) | 28-TSSOP (PW), 9.7 mm x 6.4 mm |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant (Pb-free G4 finish) | Compliant |
| Nivel MSL | 2 (per TI standard) | 2 (1 year floor life) |
| Sample Rate | — | 15 MSPS |
| Tensión de alimentación | — | 3.3 V (single supply) |
| Input Configuration | — | Single-ended / Single-ended with offset / Differential |
| Input Bandwidth | — | 150 MHz (typ) |
| Analog Input Range | — | 1 Vpp to 2 Vpp differential |
| SNR | — | 65 dB at fin = 5 MHz (typ) |
| SFDR | — | 70 dB (typ) |
| ENOB | — | [DATA_NEEDED: ENOB in bits] |
| Internal Reference | — | 1.5 V (external override supported) |
| Output Interface | — | Parallel CMOS, 12-bit straight binary |
| Latency | — | 5 clock cycles |
| Power Dissipation | — | 174 mW at 15 MSPS (typ) |
| Power-Down Mode | — | Yes (PD pin) |
| Out-of-Range Indicator | — | Yes (OTR pin) |
| Temperatura de funcionamiento | — | -40C to +85C |