XC3090L-7TQG176C vs XC3090L-6TQG176I Comparación

Comparación detallada lado a lado de XC3090L-7TQG176C por Xilinx y XC3090L-6TQG176I por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Comparación de especificaciones

Parámetro XC3090L-7TQG176C XC3090L-6TQG176I
Marca Xilinx Xilinx
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Obsolete Obsolete
Estado del stock In Stock In Stock
Precio unitario (USD) $21,20 $21,40
Family XC3000L XC3000L Low Voltage Logic Cell Array
Device XC3090L —
Logic Cells / CLBs 100 CLBs (320 F-FFs) —
Usable Gates 5,000 (typical, up to 9,000 peak) 900
User I/O Count 144 (maximum, TQG176) —
Configuration Memory SRAM (volatile, requires external PROM) SRAM (volatile, requires external configuration PROM)
Process Technology 0.8 micron CMOS CMOS, 5 V tolerant I/O on selected variants
Supply Voltage (Core) 3.0 V to 3.6 V —
Supply Voltage (I/O VCCO) 3.0 V to 3.6 V —
Logic Cell Toggle Delay approximately 1.3 to 1.5 ns (-7 speed grade) —
Rango de temperatura de funcionamiento 0C to +85C (C suffix, commercial) —
Encapsulado 176-pin TQFP (TQG176), 1.4 mm height, surface-mount TQG176 (176-pin Thin Quad Flat Pack)
Tipo de montaje Surface Mount Surface Mount
Configuration Mode Serial (master/slave) and JTAG (IEEE 1149.1) —
Nivel MSL 3 (168 hours) [DATA_NEEDED: confirm per package marking] —
Estado RoHS unknown [DATA_NEEDED: RoHS compliance]
Lead-Free / Lead Content [DATA_NEEDED] —
Configuration Clock Source Internal oscillator amplifier or external pin —
Output Drive (per I/O) 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) —
Product Type — SRAM-based FPGA
Logic Cells (CLBs) — [DATA_NEEDED: CLB count]
Speed Grade — -6 (approximately 6 ns combinatorial delay)
Supply Voltage (VCC) — 3.3 V
Operating Temperature Grade — Industrial (-40C to +85C)
Configuration Modes — 5 (Master Serial, Slave Serial, Master Parallel, Slave Parallel, Peripheral)
Boundary Scan — JTAG IEEE 1149.1
Readback — Supported
Lead-Free — [DATA_NEEDED: lead-free status]

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