XC3090L-8PCG84C vs XC3090L-125PC84C Comparación
Comparación detallada lado a lado de XC3090L-8PCG84C por Xilinx y XC3090L-125PC84C por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC3090L-8PCG84C | XC3090L-125PC84C |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $26,10 | $64,00 |
| Family | XC3000A/L Series FPGA | — |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Encapsulado | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-lead, package code QCCJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | 3.0 V to 3.6 V (typical 3.3 V) |
| Speed Grade | -8 (moderate) | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial 'C' suffix) | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | CMOS, SRAM-based |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Tipo de montaje | Surface Mount (PLCC J-Lead) | Surface Mount |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Manufacturer | — | Xilinx |
| Series | — | XC3000L |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Logic Family | — | XC3000L Low-Voltage Logic Cell Array |
| Configurable Logic Blocks (CLBs) | — | 320 |
| Equivalent Gates | — | ~5,000 |
| Flip-Flops | — | 928 |
| Maximum Toggle Frequency | — | 125 MHz |
| Terminal Form | — | J-BEND (J-lead) |
| Configuration Interface | — | Serial/parallel mode, JTAG (IEEE 1149.1) |