XC3090L-8PCG84C vs XC3090LTM-8PC84C Comparación
Comparación detallada lado a lado de XC3090L-8PCG84C por Xilinx y XC3090LTM-8PC84C por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC3090L-8PCG84C | XC3090LTM-8PC84C |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $26,10 | $43,25 |
| Family | XC3000A/L Series FPGA | XC3000L Low Voltage Logic Cell Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Encapsulado | 84-pin PLCC (J-Lead, PCG84) | 84-Pin Plastic Leaded Chip Carrier (PLCC, J-Lead) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | — |
| Speed Grade | -8 (moderate) | -8 (per suffix; see device decoder) |
| Temperatura de funcionamiento | 0 C to +70 C (commercial 'C' suffix) | -40 C to +85 C (industrial, TM suffix typically commercial/industrial) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | 0.8 um CMOS SRAM-based |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Tipo de montaje | Surface Mount (PLCC J-Lead) | Surface Mount (PLCC socket-compatible) |
| Estado RoHS | unknown | unknown |
| Lead-Free | unknown | unknown |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Logic Cells / Gates | — | ~6,000 usable gates |
| Configurable Logic Blocks (CLBs) | — | 320 |
| Configuration Memory | — | 64,160 bits (distributed SRAM) |
| Configuration Method | — | External EEPROM/EPROM/ROM/master/microprocessor mode |
| Core Supply Voltage | — | 3.0 V to 3.6 V (3.3 V typical) |
| Recuento de pines | — | 84 |
| Maximum Toggle Frequency | — | [DATA_NEEDED: specific fmax value] |
| Logic Block Delays | — | [DATA_NEEDED: typical TBU/TPIO delay] |
| I/O Standard Support | — | TTL/CMOS 3.3 V (5 V tolerant with restrictions) |
| Programming Toolchain | — | XACT / Foundation (legacy, EOL software) |