XC3090L-8TQG176C vs XC3090L-7TQG176C Comparación
Comparación detallada lado a lado de XC3090L-8TQG176C por Xilinx y XC3090L-7TQG176C por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Xilinx
XC3090L-8TQG176C - 320 CLB FPGA, 6K Gates, 80MHz, TQFP-176 | Xilinx
XC3090L-8TQG176C ObsoleteComparación de especificaciones
| Parámetro | XC3090L-8TQG176C | XC3090L-7TQG176C |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,75 | $21,20 |
| Family | XC3000L Logic Cell Array | XC3000L |
| Logic Cell Count (CLBs) | 320 | — |
| Equivalent Gates | 5,000 (6,000 max usable) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Maximum Operating Frequency | 80 MHz | — |
| Speed Grade | -8 | — |
| Encapsulado | TQFP-176 (TQG176) | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Process Technology | CMOS, low-voltage | 0.8 micron CMOS |
| Configuration Memory | Internal SRAM (reprogrammable) | SRAM (volatile, requires external PROM) |
| Configuration Modes | Serial, peripheral, master/slave parallel | — |
| I/O Standard | TTL-compatible | — |
| Temperatura de funcionamiento | Commercial (0C to +85C) | — |
| Recuento de pines | 176 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Device | — | XC3090L |
| Logic Cells / CLBs | — | 100 CLBs (320 F-FFs) |
| Usable Gates | — | 5,000 (typical, up to 9,000 peak) |
| User I/O Count | — | 144 (maximum, TQG176) |
| Supply Voltage (Core) | — | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | — | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | — | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Rango de temperatura de funcionamiento | — | 0C to +85C (C suffix, commercial) |
| Configuration Mode | — | Serial (master/slave) and JTAG (IEEE 1149.1) |
| Nivel MSL | — | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | — | [DATA_NEEDED] |
| Configuration Clock Source | — | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | — | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |