XC3090L-8TQG176C vs XC3090L-7TQG176C Comparaison
Comparaison détaillée côte à côte de XC3090L-8TQG176C par Xilinx et XC3090L-7TQG176C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Xilinx
XC3090L-8TQG176C - 320 CLB FPGA, 6K Gates, 80MHz, TQFP-176 | Xilinx
XC3090L-8TQG176C ObsoleteComparaison des spécifications
| Paramètre | XC3090L-8TQG176C | XC3090L-7TQG176C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,75 | $21,20 |
| Family | XC3000L Logic Cell Array | XC3000L |
| Logic Cell Count (CLBs) | 320 | — |
| Equivalent Gates | 5,000 (6,000 max usable) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Maximum Operating Frequency | 80 MHz | — |
| Speed Grade | -8 | — |
| Boîtier | TQFP-176 (TQG176) | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Process Technology | CMOS, low-voltage | 0.8 micron CMOS |
| Configuration Memory | Internal SRAM (reprogrammable) | SRAM (volatile, requires external PROM) |
| Configuration Modes | Serial, peripheral, master/slave parallel | — |
| I/O Standard | TTL-compatible | — |
| Température de fonctionnement | Commercial (0C to +85C) | — |
| Nombre de broches | 176 | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Device | — | XC3090L |
| Logic Cells / CLBs | — | 100 CLBs (320 F-FFs) |
| Usable Gates | — | 5,000 (typical, up to 9,000 peak) |
| User I/O Count | — | 144 (maximum, TQG176) |
| Supply Voltage (Core) | — | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | — | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | — | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Plage de température de fonctionnement | — | 0C to +85C (C suffix, commercial) |
| Configuration Mode | — | Serial (master/slave) and JTAG (IEEE 1149.1) |
| Niveau MSL | — | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | — | [DATA_NEEDED] |
| Configuration Clock Source | — | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | — | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |