XC3090LTM-125PC84C vs XC3090L-8PC84BKJ Comparación
Comparación detallada lado a lado de XC3090LTM-125PC84C por Xilinx y XC3090L-8PC84BKJ por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Xilinx
XC3090LTM-125PC84C - 5000 Gates XC3000L FPGA, 125MHz, PLCC-84 | Xilinx
XC3090LTM-125PC84C ObsoleteComparación de especificaciones
| Parámetro | XC3090LTM-125PC84C | XC3090L-8PC84BKJ |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $20,85 | $19,20 |
| Device Family | XC3000L | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Equivalent Gates | ~5000 gates | — |
| Configurable Logic Blocks (CLBs) | 320 | — |
| Flip-Flops | 928 | — |
| User I/Os | 138 | — |
| Frecuencia de reloj máxima | 125 MHz | — |
| Core Supply Voltage | 3.0 V to 3.6 V | — |
| I/O Supply Voltage | 4.75 V to 5.25 V | — |
| Encapsulado | PLCC-84 (PC84) | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) |
| Tipo de montaje | Surface Mount / Through-Hole Socket | Through-hole (PLCC socket) |
| Process Technology | CMOS, SRAM-based configuration | 5 ns CMOS SRAM |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial/industrial grade] | 0C to +70C (commercial, C suffix) |
| Configuration Method | Serial or parallel bitstream from external PROM | Serial/parallel SRAM, in-system reconfigurable |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | unknown - legacy windowed ceramic package |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Family | — | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells | — | 320 |
| Usable Gates | — | 6,000 |
| Configuration Memory | — | 64,160 bits |
| Maximum User I/O | — | 144 |
| Supply Voltage (Vcc) | — | 3.0 V to 3.6 V (low-voltage) |
| Speed Grade | — | -8 (approx. 70 MHz toggle) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Configuration Pins | — | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT |