XC6SLX4-2TQG144I vs XC6SLX9-2TQG144I Comparación
Comparación detallada lado a lado de XC6SLX4-2TQG144I por AMD y XC6SLX9-2TQG144I por AMD. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC6SLX4-2TQG144I | XC6SLX9-2TQG144I |
|---|---|---|
| Marca | AMD | AMD |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Unknown | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,19 | $16,20 |
| Device Type | Spartan-6 LX field-programmable gate array (FPGA) | — |
| Logic Cells | 3,840 cells | 9,152 |
| Block RAM | 221,184 bits | 576 Kbits (72 x 18 Kb) |
| Available I/O | 102 pins | — |
| Frecuencia de reloj máxima | 375 MHz | — |
| Tensión de alimentación | 1.14 V to 1.26 V | — |
| Speed Grade | -2 | -2 (mid-range) |
| Encapsulado | 144-pin TQFP | 144-pin TQFP (TQG144), 20 x 20 mm, 0.5 mm pitch |
| Package Body Size | 20 mm x 20 mm | — |
| Package Pitch | 0.5 mm | — |
| Process Technology | 45 nm | 45 nm low-power CMOS (9-metal copper) |
| Clocking Resources | DCM and PLL resources | — |
| Configuration Memory | SRAM-type internal latches | — |
| Memory Controller | No memory controller in XC6SLX4 | — |
| Temperature Grade | Industrial | — |
| Lead-Free Status | Lead-free | — |
| Technology | CMOS | — |
| Configuration Interface | FPGA configuration resources; detailed interface data not provided | — |
| I/O Standard | [DATA_NEEDED: supported I/O standards] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Family | — | Spartan-6 LX |
| Slices / ALMs | — | 1,430 ALMs (715 CLBs) |
| DSP Slices | — | 16 (DSP48A1) |
| Maximum User I/O | — | 102 |
| Temperatura de funcionamiento | — | -40C to +100C (Industrial) |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Bank Voltage (VCCO) | — | 1.2 V to 3.3 V |
| Memory Interfaces | — | DDR, DDR2, DDR3, LPDDR (via Memory Controller Block) |
| Clock Management | — | DCM + PLL per tile |
| Tipo de montaje | — | Surface Mount |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |
| Estado RoHS | — | RoHS Compliant (Lead Free) |