XC6SLX45-2FGG484I vs XC6SLX25-2FGG484I Comparación
Comparación detallada lado a lado de XC6SLX45-2FGG484I por AMD y XC6SLX25-2FGG484I por AMD. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC6SLX45-2FGG484I | XC6SLX25-2FGG484I |
|---|---|---|
| Marca | AMD | AMD |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $65,10 | $17,50 |
| Family | Spartan-6 LX | Spartan-6 LX |
| Logic Cells | 43,661 | 24051 |
| Logic Slices | 6,822 | — |
| Flip-Flops | 54,576 | — |
| Block RAM | 2,138,112 bits (2,088 Kb/s) | 958464 bits |
| DSP Slices (DSP48A1) | 58 | — |
| Maximum User I/O | 316 | — |
| Encapsulado | 484-ball BGA (FBGA-484) | 484-BBGA (23x23 mm, 1 mm pitch) |
| Package Dimensions | 23 x 23 mm, 1.0 mm ball pitch | — |
| Speed Grade | -2 | -2 |
| Operating Temperature (I grade) | -40C to +100C (industrial) | — |
| Process Technology | 45 nm low-power CMOS | 45 nm CMOS |
| Supply Voltage Core | 1.2 V typical | — |
| Clock Management Tiles | 6 CMT (4 DCM + 2 PLL) | — |
| Maximum I/O Speed | 800 Mbps LVDS | — |
| Memory Interface Support | DDR, DDR2, DDR3, LPDDR | — |
| Configuration Memory | AES-256 bitstream encryption | — |
| RoHS Compliance | Lead-free / RoHS compliant | — |
| DSP Slices | — | 52 |
| User I/O | — | 266 |
| Core Voltage | — | 1.2 V |
| Internal Frequency | — | 500 MHz |
| Temperatura de funcionamiento | — | -40°C to +100°C |
| Tipo de montaje | — | Surface Mount |
| RoHS | — | Compliant |
| Lead Free | — | Yes |
| Configuration Modes | — | Master SPI, Slave SelectMAP, JTAG |