XC6SLX9-3TQG144I vs XC6SLX9-2TQG144I Comparación
Comparación detallada lado a lado de XC6SLX9-3TQG144I por AMD y XC6SLX9-2TQG144I por AMD. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC6SLX9-3TQG144I | XC6SLX9-2TQG144I |
|---|---|---|
| Marca | AMD | AMD |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $16,20 |
| Device Type | FPGA | — |
| FPGA Family | Spartan-6 LX | — |
| Logic Cells | 9,152 logic cells | 9,152 |
| I/O Count | 102 I/O | — |
| Encapsulado | 144-LQFP | 144-pin TQFP (TQG144), 20 x 20 mm, 0.5 mm pitch |
| Recuento de pines | 144 pins | — |
| Speed Grade | -3 | -2 (mid-range) |
| Variant Suffix | I | — |
| Tipo de montaje | Surface mount | Surface Mount |
| Temperature Grade | Industrial temperature variant indicated by I suffix; exact temperature range not provided | — |
| Internal Frequency | 667 MHz | — |
| Temperatura de funcionamiento | 0 C to 85 C (32 F to 185 F) | -40C to +100C (Industrial) |
| Tensión de alimentación | [DATA_NEEDED: supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type] | — |
| Block RAM | [DATA_NEEDED: block RAM quantity] | 576 Kbits (72 x 18 Kb) |
| DSP Slices | [DATA_NEEDED: DSP slice quantity] | 16 (DSP48A1) |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Estado RoHS | unknown | RoHS Compliant (Lead Free) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Family | — | Spartan-6 LX |
| Slices / ALMs | — | 1,430 ALMs (715 CLBs) |
| Maximum User I/O | — | 102 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Bank Voltage (VCCO) | — | 1.2 V to 3.3 V |
| Process Technology | — | 45 nm low-power CMOS (9-metal copper) |
| Memory Interfaces | — | DDR, DDR2, DDR3, LPDDR (via Memory Controller Block) |
| Clock Management | — | DCM + PLL per tile |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |