XC6SLX9-3TQG144I vs XC6SLX9-2TQG144I Comparaison
Comparaison détaillée côte à côte de XC6SLX9-3TQG144I par AMD et XC6SLX9-2TQG144I par AMD. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC6SLX9-3TQG144I | XC6SLX9-2TQG144I |
|---|---|---|
| Marque | AMD | AMD |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $16,20 |
| Device Type | FPGA | — |
| FPGA Family | Spartan-6 LX | — |
| Logic Cells | 9,152 logic cells | 9,152 |
| I/O Count | 102 I/O | — |
| Boîtier | 144-LQFP | 144-pin TQFP (TQG144), 20 x 20 mm, 0.5 mm pitch |
| Nombre de broches | 144 pins | — |
| Speed Grade | -3 | -2 (mid-range) |
| Variant Suffix | I | — |
| Type de montage | Surface mount | Surface Mount |
| Temperature Grade | Industrial temperature variant indicated by I suffix; exact temperature range not provided | — |
| Internal Frequency | 667 MHz | — |
| Température de fonctionnement | 0 C to 85 C (32 F to 185 F) | -40C to +100C (Industrial) |
| Tension d'alimentation | [DATA_NEEDED: supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type] | — |
| Block RAM | [DATA_NEEDED: block RAM quantity] | 576 Kbits (72 x 18 Kb) |
| DSP Slices | [DATA_NEEDED: DSP slice quantity] | 16 (DSP48A1) |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Statut RoHS | unknown | RoHS Compliant (Lead Free) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Family | — | Spartan-6 LX |
| Slices / ALMs | — | 1,430 ALMs (715 CLBs) |
| Maximum User I/O | — | 102 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Bank Voltage (VCCO) | — | 1.2 V to 3.3 V |
| Process Technology | — | 45 nm low-power CMOS (9-metal copper) |
| Memory Interfaces | — | DDR, DDR2, DDR3, LPDDR (via Memory Controller Block) |
| Clock Management | — | DCM + PLL per tile |
| Niveau MSL | — | 3 (per JEDEC J-STD-020) |