74LVC1G123DC - Single Retriggerable Monostable Multivibrator | Nexperia
N.º de pieza: 74LVC1G123DC ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $0.55 | $0,55 |
| 10 | $0.48 | $4,80 |
| 100 | $0.38 | $38,00 |
| 500 | $0.31 | $155,00 |
| 1.000 | $0.26 | $260,00 |
74LVC1G123DC Descripción general
What is a monostable multivibrator? A monostable multivibrator (commonly called a one-shot) is a sequential logic element with one stable state and one temporary state. Upon receiving a valid trigger edge, the circuit switches to the temporary state for a programmed interval, then returns to the stable state. The 74LVC1G123 belongs to the LVC (Low-Voltage CMOS) logic family within the broader CMOS logic IC hierarchy, occupying the specialty-logic sub-category alongside multivibrators, Schmitt triggers, and buffers.
Key features include three pulse-width control methods: external R-C programming, retriggering via the gated active-LOW A or active-HIGH B input, and direct reset via the CLR input. Schmitt-trigger action on both trigger inputs (A and B) makes the device highly immune to slow or noisy edges - typical hysteresis of approximately 0.8 V at 3.3 V VCC rejects input noise of several hundred millivolts. The wide 1.65 V to 5.5 V supply range enables direct interfacing between 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without external level shifters.
The architecture combines an edge-triggered control gate, a precision pulse-width timing core, and a totem-pole CMOS output stage capable of sourcing/sinking up to 32 mA at 3.3 V. Ioff partial-power-down support means the device can be inserted into live buses safely when VCC is removed - a critical feature for hot-swap or multi-rail designs. The Schmitt hysteresis on both trigger inputs delivers reliable operation in electrically noisy industrial environments where standard CMOS gates would double-trigger.
Typical applications include pulse generation in industrial control, watchdog timer circuits, debouncing mechanical switches and rotary encoders, missing-pulse detection in motor-control feedback loops, and reset pulse shaping in microcontroller-based systems. The 5 V tolerance on outputs (when VCC = 3.3 V) also makes it useful for legacy 5 V peripheral interfacing in mixed-voltage systems.
When designing with the 74LVC1G123DC, select the external REXT and CEXT using the datasheet pulse-width formula tw = REXT × CEXT × ln(2) ≈ 0.69 × REXT × CEXT and verify timing across process, voltage, and temperature corners. Place CEXT as close as possible to the device pins to minimize parasitic capacitance that would otherwise skew the timing accuracy.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternativas directas para 74LVC1G123DC — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
74LVC1G123DC,125
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
74LVC1G123DC-Q100H
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LVC1G123DCUT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LVC1G123DBVR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
74LVC1G123DC Valores máximos y características eléctricas
| Función | Single retriggerable monostable multivibrator with Schmitt-trigger inputs |
| Logic Family | 74LVC (Low-Voltage CMOS) |
| Supply Voltage (VCC) | 1.65 V to 5.5 V |
| Typical Propagation Delay (tpd) | 5.3 ns at 5 V VCC |
| Trigger Inputs | A (active-LOW gated) and B (active-HIGH) |
| Schmitt-Trigger Inputs | Yes (on A and B) |
| Tipo de salida | CMOS totem-pole (push-pull) |
| Output Drive Capability | ±32 mA at 3.3 V VCC |
| Output Pulse Width Control | External REXT and CEXT |
| Retrigger Capability | Yes (via A or B inputs) |
| Direct Reset (CLR) | Yes |
| Ioff Partial-Power-Down Support | Yes |
| Rango de temperatura de funcionamiento | -40 °C to +125 °C |
| Encapsulado | 8-VSSOP (DC) — 2.0 mm × 3.1 mm body |
| Tipo de montaje | Surface Mount |
| Nivel MSL | 1 (per JEDEC J-STD-020) |
| Estado RoHS | Compliant |
| Lead-Free / Halogen-Free | Yes (Nexperia green standard) |
Configuración de pines de 74LVC1G123DC
| Pin 1 | A — Trigger input A, active-LOW gated edge (Schmitt-trigger) |
| Pin 2 | B — Trigger input B, active-HIGH (Schmitt-trigger) |
| Pin 3 | CLR — Direct reset, active-LOW |
| Pin 4 | GND — Ground (0 V reference) |
| Pin 5 | Q — Monostable output, totem-pole CMOS |
| Pin 6 | CEXT — External timing capacitor pin |
| Pin 7 | REXT/CEXT — External timing resistor and capacitor pin |
| Pin 8 | VCC — Positive supply voltage (1.65 V to 5.5 V) |
Aplicaciones típicas
74LVC1G123DC es adecuado para 6 aplicacións: Industrial Control Pulse Generation, Mechanical Switch Debouncing, Watchdog Timer Circuit, Missing-Pulse Detection, Reset Pulse Shaping, Portable Consumer Electronics.
Industrial Control Pulse Generation
The 74LVC1G123DC generates precise trigger pulses in industrial PLCs and motor drives, where its 1.65 V to 5.5 V VCC range and ±32 mA totem-pole output drive 24 V opto-isolators via small signal transistors. The Schmitt-trigger inputs reject electrical noise from switching power stages, ensuring one trigger produces one pulse even on long cables. The retriggerable architecture extends pulse width on demand, useful for missing-pulse detection in conveyor feedback loops.
Recomendado
Mechanical Switch Debouncing
The 74LVC1G123DC debounces mechanical switches and rotary encoders by outputting a single clean pulse per valid actuation, eliminating contact bounce that would otherwise cause false counting. The Schmitt-trigger hysteresis of approximately 0.8 V at 3.3 V rejects bounce transients below the threshold. REXT and CEXT program a 5 to 20 ms output pulse to mask typical 1 to 5 ms switch bounce, with retrigger capability extending the pulse if the switch re-engages during the window.
Recomendado
Watchdog Timer Circuit
The 74LVC1G123DC implements a microcontroller watchdog timer by retriggering on each valid WDT service pulse; if the MCU hangs and stops servicing, the Q output transitions and generates a reset pulse via the CLR pin. The wide VCC range of 1.65 V to 5.5 V allows operation directly from 1.8 V or 3.3 V MCU rails. The Ioff partial-power-down support is essential in battery-backed systems where the multivibrator remains powered but the MCU is in deep sleep.
Recomendado
Missing-Pulse Detection
The 74LVC1G123DC detects missing pulses in motor speed feedback by retriggering on each tachometer pulse; if a pulse is skipped, the timer expires and the Q output toggles, signalling a fault to the controller. The retriggerable architecture is critical because variable-speed motors produce pulse trains with changing periods. The 5.3 ns typical propagation delay at 5 V enables reliable detection of pulse trains up to several hundred kHz, with timing margin set by REXT × CEXT.
Recomendado
Reset Pulse Shaping
The 74LVC1G123DC shapes microcontroller reset pulses by generating a clean, programmable-width active-LOW pulse on power-up or brown-out events. The retriggerable input allows manual reset button inputs without debounce hardware, and the direct CLR pin permits external supervisory circuits to override the timing. The 8-VSSOP package fits alongside small microcontrollers in space-constrained designs, and the Ioff feature protects against bus contention during incomplete power-up sequences.
Recomendado
Portable Consumer Electronics
The 74LVC1G123DC delivers timing functions in portable consumer devices such as wearables, toys, and remote controls where its 1.65 V to 5.5 V VCC range supports direct battery operation and its tiny 8-VSSOP package minimizes PCB footprint. The retriggerable one-shot function is ideal for button-press detection, motion-sensor pulse extension, and LED driver timing. Quiescent current is typically under 10 µA, making it suitable for battery-powered applications where standby drain matters.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para 74LVC1G123DC — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | 74LVC1G123DC,125 | 74LVC1G123DC-Q100H | SN74LVC1G123DCUT |
|---|---|---|---|---|
| Package | 8-VSSOP (DC) | 8-VSSOP (DC) - same | 8-VSSOP (DC) - same | 8-VSSOP (DCUT) - same |
| Brand | Nexperia | Nexperia | Nexperia | Texas Instruments |
| VCC Range | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 1.65 V to 5.5 V |
| Typical Propagation Delay | 5.3 ns at 5 V | 5.3 ns at 5 V | 5.3 ns at 5 V | 18.5 ns max at 3.3 V |
| AEC-Q100 Qualified | No | No | Yes (automotive) | No |
| Schmitt-Trigger Inputs | Yes (A and B) | Yes (A and B) | Yes (A and B) | Yes (A and B) |
| Ioff Partial-Power-Down | Yes | Yes | Yes | Yes |
| Operating Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C (AEC-Q100) | -40 °C to +125 °C |
| Lifecycle Status | Active | Active | Active | Active |
Diferenciadores clave
- Industry-standard 8-VSSOP (DC) footprint with wide second-source availability (frente a 74HC123 (16-SOIC))
- Lower propagation delay for timing-critical pulse generation (frente a SN74LVC1G123DCUT)
- Automotive-qualified variant available in identical package (frente a 74LVC1G123DC-Q100H)
- Integrated Ioff partial-power-down protection (frente a 74HC123 (no Ioff))
Notas de diseño
The 74LVC1G123DC quiescent current is typically under 10 µA at 3.3 V VCC, but during output transitions the supply current spikes as the totem-pole stage drives the load. Estimated: at 1 MHz trigger rate with a 50 pF load, average ICC rises to roughly 200 µA. Decouple VCC with a 100 nF ceramic capacitor placed within 5 mm of the VCC pin (pin 8), plus a 10 µF bulk capacitor if the device shares a rail with switching converters. The Ioff feature prevents backflow current when VCC is removed, but does not eliminate the need for proper supply sequencing in multi-rail systems.
Place the external timing capacitor CEXT as close as physically possible to the CEXT pin (pin 6) and REXT/CEXT pin (pin 7) to minimize parasitic PCB capacitance. Estimated: each 5 pF of stray capacitance adds approximately 1 to 2 % error to the programmed pulse width for a 100 ns timing range. Use a ground pour under the device to shield the timing components from switching noise on adjacent traces. Keep digital signal traces away from the CEXT pin to prevent injected charge from disturbing the timing accuracy.
Do not exceed the absolute maximum VCC rating of 6.5 V on the 74LVC1G123DC — the part is rated for 5.5 V operation but tolerates brief transients up to 6.5 V. Ensure that REXT is selected to keep the discharge current below 50 mA peak; typical REXT values range from 1 kΩ to 1 MΩ depending on the desired pulse width and CEXT value. The CLR input is asynchronous — deassert CLR before retriggering if clean retrigger behavior is required. Verify that the trigger pulse width on A or B exceeds the minimum specified value (typically 5 ns) to guarantee recognition.
The Schmitt-trigger inputs on A (active-LOW gated) and B (active-HIGH) provide approximately 0.8 V of hysteresis at 3.3 V VCC, rejecting input noise of several hundred millivolts. For ultra-noisy industrial environments, add an external RC low-pass filter on the trigger input with a time constant well below the minimum trigger pulse width. The Q output totem-pole stage can drive ±32 mA at 3.3 V — adequate for direct LED drive, but for higher-current loads use a separate buffer such as SN74LVC1G07DBVR.
Información de cumplimiento
Nexperia 74LVC1G123DC,125 is RoHS and REACH compliant per Nexperia product page. Standard part is not AEC-Q100 — choose 74LVC1G123DC-Q100H for automotive. Halogen-free per Nexperia green-compound policy.
