ADC1613D080HN-C18 - Dual 16-bit 80MSPS ADC w/ JESD204A | Renesas
N.º de pieza: ADC1613D080HN-C18 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $35.2 | $352,00 |
| 100 | $30.75 | $3.075,00 |
| 500 | $26.4 | $13.200,00 |
| 1.000 | $23.1 | $23.100,00 |
ADC1613D080HN-C18 Descripción general
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog signal into a discrete-time, discrete-amplitude digital code. The dual pipelined architecture used in the ADC1613D080HN-C18 enables simultaneous sampling of two analog inputs at high speed while maintaining wide spurious-free dynamic range (SFDR) and low integral non-linearity (INL). Pipelined ADCs sit hierarchically between successive-approximation (SAR) ADCs and flash ADCs, offering the speed-resolution trade-off required for communications, imaging, and instrumentation. A JESD204A serial interface further standardizes the high-speed data output link to FPGAs or DSPs.
Key features include dual 16-bit resolution, 80 MSPS maximum sample rate per channel, 65/80/105/125 MSPS device family variants, on-chip reference and sample-and-hold, low-voltage differential signaling (LVDS) and JESD204A-coded serial outputs, and a single 3.0 V to 3.6 V analog supply. The HVQFN-56 (8x8 mm) package provides an exposed thermal pad for low junction-to-board thermal resistance, allowing continuous dual-channel operation at full speed without external heatsinking.
The pipelined architecture uses multi-bit per stage gain and digital error correction, with a dedicated reference buffer to maintain low-knee noise across temperature. Internal calibration logic corrects for inter-stage gain and offset mismatches at power-up, supporting the SFDR performance claimed in the manufacturer datasheet. The device supports both full-scale input ranges via an internal reference, simplifying bill-of-materials and reducing external component count.
Typical applications include multi-channel communications receivers, medical imaging front-ends (ultrasound beamformers), digital oscilloscopes, radar signal processing, and high-density data acquisition modules. The dual-channel configuration is particularly suited to I/Q baseband sampling and diversity receiver paths.
When designing with this part, ensure the JESD204A link parameters (lane count, K, F, M) are consistent between the ADC and the receiving FPGA logic. Place the decoupling network as close as possible to the supply pins and provide a solid ground plane under the exposed pad for stable thermal and electrical behavior.
This page synthesizes Renesas distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternativas directas para ADC1613D080HN-C18 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con ADC1613D080HN-C18 (mismo factor de forma y huella) — difiere en Number of Channels, Package, Input Type, Resolution, Digital Supply Voltage.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
ADC1413D080HN-C1
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADC1413D125HN-C1
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADC1613D125HN-C18
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADC1610S125HN-C1
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$18.95 / unidad
Ver hoja de datos →ADC1112D125HN-C18
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$9.48 / unidad
Ver hoja de datos →ADC1613D080HN-C18 Valores máximos y características eléctricas
| Resolución | 16 bit |
| Number of Channels | 2 |
| Architecture | Pipelined |
| Sample Rate (max per channel) | 80 MSPS |
| Family Sample Rate Variants | 65 / 80 / 105 / 125 MSPS |
| Data Interface | Serial JESD204A |
| Input Type | Differential analog inputs |
| Analog Supply Voltage | 3.0 V to 3.6 V |
| Digital Supply Voltage | 3.0 V to 3.6 V |
| Encapsulado | 56-HVQFN (8x8 mm) with exposed pad |
| Tipo de montaje | Surface Mount |
| Nivel MSL | 3 (per manufacturer handling guidelines) |
| Lead-Free / RoHS | Yes (per manufacturer datasheet) |
| Internal Reference | Yes |
Configuración de pines de ADC1613D080HN-C18
| Pin 1 | VDDA — Analog supply voltage (3.3 V) |
| Pin 2 | GNDA — Analog ground |
| Pin 3 | INA+ — Channel A differential positive input |
| Pin 4 | INA- — Channel A differential negative input |
| Pin 5 | INB+ — Channel B differential positive input |
| Pin 6 | INB- — Channel B differential negative input |
| Pin 7 | VCM — Common-mode voltage output |
| Pin 8 | REFT — Top reference decoupling |
| Pin 9 | REFB — Bottom reference decoupling |
| Pin 10 | GNDA — Analog ground |
| Pin 11 | VDDA — Analog supply voltage (3.3 V) |
| Pin 12 | BIAS — Bias current setting resistor |
| Pin 13 | CLK+ — Differential clock input positive |
| Pin 14 | CLK- — Differential clock input negative |
| Pin 15 | GNDD — Digital ground |
| Pin 16 | VDDD — Digital supply voltage (3.3 V) |
| Pin 17 | SYNCIN — JESD204A synchronization input |
| Pin 18 | SYNCOUT — JESD204A synchronization output |
| Pin 19 | D0+ — JESD204A serial lane 0 positive |
| Pin 20 | D0- — JESD204A serial lane 0 negative |
| Pin 21 | GNDD — Digital ground |
| Pin 22 | VDDD — Digital supply voltage (3.3 V) |
| Pin 23 | D1+ — JESD204A serial lane 1 positive |
| Pin 24 | D1- — JESD204A serial lane 1 negative |
| Pin 25 | GNDD — Digital ground |
| Pin 26 | SCLK — Serial configuration clock |
| Pin 27 | SDIO — Serial configuration data I/O |
| Pin 28 | CSB — Serial configuration chip select (active low) |
| Pin 29 | RESETB — Reset (active low) |
| Pin 30 | PDN — Power-down control |
| Pin 31 | GNDA — Analog ground |
| Pin 32 | VDDA — Analog supply voltage (3.3 V) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | GNDA — Analog ground |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | GNDA — Analog ground |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | GNDA — Analog ground |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | GNDA — Analog ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | GNDA — Analog ground |
| Pin 54 | GNDA — Analog ground |
| Pin 55 | GNDA — Analog ground |
| Pin 56 | EP — Exposed pad - thermal/ground, must be soldered to PCB ground plane |
Aplicaciones típicas
ADC1613D080HN-C18 es adecuado para 6 aplicacións: Multi-Channel Communications Receiver, Medical Ultrasound Beamformer, Digital Oscilloscope Channel Card, Radar Signal Processing Front-End, Industrial Data Acquisition Module, Software-Defined Radio Baseband.
Multi-Channel Communications Receiver
The ADC1613D080HN-C18's dual 16-bit 80 MSPS channels and JESD204A-coded LVDS output are well suited for diversity and I/Q baseband sampling in wireless receivers. Two channels sample the in-phase and quadrature rails of a complex IF, while the deterministic JESD link offloads the resulting 160 MSPS aggregate stream to an FPGA baseband processor. Differential inputs reject common-mode noise from LNA/Mixer stages, and the internal reference simplifies the bill of materials on the RF daughter card.
Recomendado
Medical Ultrasound Beamformer
In ultrasound front-ends, the ADC1613D080HN-C18's 16-bit resolution at 80 MSPS provides the dynamic range required to digitize reflected echoes from deep tissue without sacrificing spurious-free dynamic range. Each dual channel can be assigned to adjacent transducer channels in a tile array, while the JESD204A output concentrates data into a small number of serial lanes to keep the probe head flex cable thin. The HVQFN-56 (8x8 mm) package fits behind high-density transducer arrays.
Recomendado
Digital Oscilloscope Channel Card
The ADC1613D080HN-C18 suits 100-200 MHz bandwidth oscilloscope channel cards where 16-bit resolution preserves vertical detail on small signals alongside large dynamic excursions. The dual pipelined architecture simultaneously samples CH1 and CH2 (or CH3 and CH4), reducing total IC count on dense 4-channel front-end boards. JESD204A offloads the 200 MSPS aggregate data through one or two serial lanes to a downstream FPGA DSP block, where triggering and decimation occur.
Recomendado
Radar Signal Processing Front-End
In phased-array radar and Lidar receiver electronics, the ADC1613D080HN-C18 captures matched-filter outputs from multiple receive channels with the linearity needed to preserve signal-to-clutter ratio. Dual simultaneous sampling maintains phase coherence between paired antennas, while the JESD204A coded link synchronizes multi-ADC aggregation across the array. The HVQFN-56 footprint allows dense placement near the RF down-conversion chain.
Recomendado
Industrial Data Acquisition Module
The ADC1613D080HN-C18 fits dense industrial data acquisition cards where two 16-bit 80 MSPS channels digitize vibration, sonar, or process-control signals simultaneously. The 3.3 V single-supply operation simplifies power tree design, while JESD204A over a small number of LVDS lanes reduces FPGA pin count per channel. Industrial temperature variants and on-chip calibration support deployment in factory-floor enclosures.
Recomendado
Software-Defined Radio Baseband
The ADC1613D080HN-C18's dual simultaneous 16-bit 80 MSPS channels suit SDR baseband digitization, where I and Q paths must be sampled in lockstep to preserve quadrature balance. The JESD204A serial interface allows multiple ADC1613D080HN-C18 parts to be aggregated into a single FPGA, scaling channel count without proportional FPGA pin growth. Differential inputs reject switching noise from the upstream digital baseband block, supporting low bit-error-rate demodulation.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para ADC1613D080HN-C18 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | ADC1413D080HN-C1 | ADC1413D125HN-C1 | ADC1613D125HN-C18 | ADC1610S125HN-C1 | ADC1112D125HN-C18 |
|---|---|---|---|---|---|---|
| Package | 56-HVQFN (8x8 mm) | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same |
| Brand | Renesas Electronics | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same |
| Resolution | 16 bit | 14 bit | 14 bit | 16 bit | 16 bit | 11 bit |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 2 |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Interface | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
Diferenciadores clave
- Dual-channel simultaneous sampling at full 80 MSPS (frente a ADC1610S125HN-C1)
- Higher 16-bit resolution across the same footprint (frente a ADC1413D080HN-C1)
- Lower 80 MSPS sample rate vs 125 MSPS family member (frente a ADC1613D125HN-C18)
Notas de diseño
The ADC1613D080HN-C18 requires clean, low-noise analog and digital supplies in the 3.0-3.6 V range. Place a ferrite bead between VDDA and VDDD planes, and decouple each pin with 0.1 uF X7R ceramic in parallel with 10 uF bulk. Use a dedicated LDO upstream (e.g. ADP3339 or TPS7A47xx) to reject switching noise from upstream DC-DC converters; ripple above 10 mVpp on VDDA degrades SFDR by approximately 1-2 dB per octave.
Solder the exposed thermal pad (pin 56) to a continuous ground plane with at least 9 thermal vias (3x3 grid, 0.3 mm drill) for junction-to-board thermal resistance. Maintain a 50-ohm controlled-impedance differential pair layout for CLK+/-, D0+/-, and D1+/- lanes; use length-matched traces within 1 mm to satisfy JESD204A setup/hold. Keep analog input traces short and away from digital output lanes to prevent coupling into the front-end sampling path.
Configure JESD204A link parameters (L, K, M, F) to match the receiving FPGA logic IP core. Mismatched K between the ADC and FPGA causes intermittent frame alignment failures visible as dropped samples. Verify deterministic latency using SYNCIN/SYNCOUT handshaking before enabling downstream processing.
Avoid placing bypass capacitors on REFT and REFB more than 2 mm from their respective pins - long traces introduce series inductance that destabilizes the internal reference loop and causes SFDR roll-off above 30 MHz input. Also ensure the BIAS resistor value matches the manufacturer datasheet (typically 10 kohm 1%); using wrong values shifts the internal bias point and degrades linearity.
Información de cumplimiento
RoHS / REACH compliance and lead-free / halogen-free status per Renesas manufacturer datasheet. AEC-Q100 not applicable - this part targets communications and instrumentation, not automotive safety.
