ADC1613D080HN-C18 - Dual 16-bit 80MSPS ADC w/ JESD204A | Renesas
부품 번호: ADC1613D080HN-C18 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $30.75 | $3,075.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
ADC1613D080HN-C18 개요
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog signal into a discrete-time, discrete-amplitude digital code. The dual pipelined architecture used in the ADC1613D080HN-C18 enables simultaneous sampling of two analog inputs at high speed while maintaining wide spurious-free dynamic range (SFDR) and low integral non-linearity (INL). Pipelined ADCs sit hierarchically between successive-approximation (SAR) ADCs and flash ADCs, offering the speed-resolution trade-off required for communications, imaging, and instrumentation. A JESD204A serial interface further standardizes the high-speed data output link to FPGAs or DSPs.
Key features include dual 16-bit resolution, 80 MSPS maximum sample rate per channel, 65/80/105/125 MSPS device family variants, on-chip reference and sample-and-hold, low-voltage differential signaling (LVDS) and JESD204A-coded serial outputs, and a single 3.0 V to 3.6 V analog supply. The HVQFN-56 (8x8 mm) package provides an exposed thermal pad for low junction-to-board thermal resistance, allowing continuous dual-channel operation at full speed without external heatsinking.
The pipelined architecture uses multi-bit per stage gain and digital error correction, with a dedicated reference buffer to maintain low-knee noise across temperature. Internal calibration logic corrects for inter-stage gain and offset mismatches at power-up, supporting the SFDR performance claimed in the manufacturer datasheet. The device supports both full-scale input ranges via an internal reference, simplifying bill-of-materials and reducing external component count.
Typical applications include multi-channel communications receivers, medical imaging front-ends (ultrasound beamformers), digital oscilloscopes, radar signal processing, and high-density data acquisition modules. The dual-channel configuration is particularly suited to I/Q baseband sampling and diversity receiver paths.
When designing with this part, ensure the JESD204A link parameters (lane count, K, F, M) are consistent between the ADC and the receiving FPGA logic. Place the decoupling network as close as possible to the supply pins and provide a solid ground plane under the exposed pad for stable thermal and electrical behavior.
This page synthesizes Renesas distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
드롭인 대체품: ADC1613D080HN-C18 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1613D080HN-C18 (동일 폼 팩터 및 풋프린트) — 차이점: Number of Channels, Package, Input Type, Resolution, Digital Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1413D080HN-C1
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADC1413D125HN-C1
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADC1613D125HN-C18
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADC1610S125HN-C1
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$18.95 / 개
데이터시트 보기 →ADC1112D125HN-C18
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$9.48 / 개
데이터시트 보기 →ADC1613D080HN-C18 최대 정격 & 전기적 특성
| 분해능 | 16 bit |
| Number of Channels | 2 |
| Architecture | Pipelined |
| Sample Rate (max per channel) | 80 MSPS |
| Family Sample Rate Variants | 65 / 80 / 105 / 125 MSPS |
| Data Interface | Serial JESD204A |
| Input Type | Differential analog inputs |
| Analog Supply Voltage | 3.0 V to 3.6 V |
| Digital Supply Voltage | 3.0 V to 3.6 V |
| 패키지 | 56-HVQFN (8x8 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 (per manufacturer handling guidelines) |
| Lead-Free / RoHS | Yes (per manufacturer datasheet) |
| Internal Reference | Yes |
ADC1613D080HN-C18 핀 구성
| 핀 1 | VDDA — Analog supply voltage (3.3 V) |
| 핀 2 | GNDA — Analog ground |
| 핀 3 | INA+ — Channel A differential positive input |
| 핀 4 | INA- — Channel A differential negative input |
| 핀 5 | INB+ — Channel B differential positive input |
| 핀 6 | INB- — Channel B differential negative input |
| 핀 7 | VCM — Common-mode voltage output |
| 핀 8 | REFT — Top reference decoupling |
| 핀 9 | REFB — Bottom reference decoupling |
| 핀 10 | GNDA — Analog ground |
| 핀 11 | VDDA — Analog supply voltage (3.3 V) |
| 핀 12 | BIAS — Bias current setting resistor |
| 핀 13 | CLK+ — Differential clock input positive |
| 핀 14 | CLK- — Differential clock input negative |
| 핀 15 | GNDD — Digital ground |
| 핀 16 | VDDD — Digital supply voltage (3.3 V) |
| 핀 17 | SYNCIN — JESD204A synchronization input |
| 핀 18 | SYNCOUT — JESD204A synchronization output |
| 핀 19 | D0+ — JESD204A serial lane 0 positive |
| 핀 20 | D0- — JESD204A serial lane 0 negative |
| 핀 21 | GNDD — Digital ground |
| 핀 22 | VDDD — Digital supply voltage (3.3 V) |
| 핀 23 | D1+ — JESD204A serial lane 1 positive |
| 핀 24 | D1- — JESD204A serial lane 1 negative |
| 핀 25 | GNDD — Digital ground |
| 핀 26 | SCLK — Serial configuration clock |
| 핀 27 | SDIO — Serial configuration data I/O |
| 핀 28 | CSB — Serial configuration chip select (active low) |
| 핀 29 | RESETB — Reset (active low) |
| 핀 30 | PDN — Power-down control |
| 핀 31 | GNDA — Analog ground |
| 핀 32 | VDDA — Analog supply voltage (3.3 V) |
| 핀 33 | NC — Not connected (per datasheet) |
| 핀 34 | NC — Not connected (per datasheet) |
| 핀 35 | NC — Not connected (per datasheet) |
| 핀 36 | GNDA — Analog ground |
| 핀 37 | NC — Not connected (per datasheet) |
| 핀 38 | NC — Not connected (per datasheet) |
| 핀 39 | NC — Not connected (per datasheet) |
| 핀 40 | GNDA — Analog ground |
| 핀 41 | NC — Not connected (per datasheet) |
| 핀 42 | NC — Not connected (per datasheet) |
| 핀 43 | GNDA — Analog ground |
| 핀 44 | NC — Not connected (per datasheet) |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | GNDA — Analog ground |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | NC — Not connected (per datasheet) |
| 핀 49 | NC — Not connected (per datasheet) |
| 핀 50 | NC — Not connected (per datasheet) |
| 핀 51 | NC — Not connected (per datasheet) |
| 핀 52 | NC — Not connected (per datasheet) |
| 핀 53 | GNDA — Analog ground |
| 핀 54 | GNDA — Analog ground |
| 핀 55 | GNDA — Analog ground |
| 핀 56 | EP — Exposed pad - thermal/ground, must be soldered to PCB ground plane |
일반적인 애플리케이션
ADC1613D080HN-C18 적합 용도: 6 애플리케이션s: Multi-Channel Communications Receiver, Medical Ultrasound Beamformer, Digital Oscilloscope Channel Card, Radar Signal Processing Front-End, Industrial Data Acquisition Module, Software-Defined Radio Baseband.
Multi-Channel Communications Receiver
The ADC1613D080HN-C18's dual 16-bit 80 MSPS channels and JESD204A-coded LVDS output are well suited for diversity and I/Q baseband sampling in wireless receivers. Two channels sample the in-phase and quadrature rails of a complex IF, while the deterministic JESD link offloads the resulting 160 MSPS aggregate stream to an FPGA baseband processor. Differential inputs reject common-mode noise from LNA/Mixer stages, and the internal reference simplifies the bill of materials on the RF daughter card.
추천
Medical Ultrasound Beamformer
In ultrasound front-ends, the ADC1613D080HN-C18's 16-bit resolution at 80 MSPS provides the dynamic range required to digitize reflected echoes from deep tissue without sacrificing spurious-free dynamic range. Each dual channel can be assigned to adjacent transducer channels in a tile array, while the JESD204A output concentrates data into a small number of serial lanes to keep the probe head flex cable thin. The HVQFN-56 (8x8 mm) package fits behind high-density transducer arrays.
추천
Digital Oscilloscope Channel Card
The ADC1613D080HN-C18 suits 100-200 MHz bandwidth oscilloscope channel cards where 16-bit resolution preserves vertical detail on small signals alongside large dynamic excursions. The dual pipelined architecture simultaneously samples CH1 and CH2 (or CH3 and CH4), reducing total IC count on dense 4-channel front-end boards. JESD204A offloads the 200 MSPS aggregate data through one or two serial lanes to a downstream FPGA DSP block, where triggering and decimation occur.
추천
Radar Signal Processing Front-End
In phased-array radar and Lidar receiver electronics, the ADC1613D080HN-C18 captures matched-filter outputs from multiple receive channels with the linearity needed to preserve signal-to-clutter ratio. Dual simultaneous sampling maintains phase coherence between paired antennas, while the JESD204A coded link synchronizes multi-ADC aggregation across the array. The HVQFN-56 footprint allows dense placement near the RF down-conversion chain.
추천
Industrial Data Acquisition Module
The ADC1613D080HN-C18 fits dense industrial data acquisition cards where two 16-bit 80 MSPS channels digitize vibration, sonar, or process-control signals simultaneously. The 3.3 V single-supply operation simplifies power tree design, while JESD204A over a small number of LVDS lanes reduces FPGA pin count per channel. Industrial temperature variants and on-chip calibration support deployment in factory-floor enclosures.
추천
Software-Defined Radio Baseband
The ADC1613D080HN-C18's dual simultaneous 16-bit 80 MSPS channels suit SDR baseband digitization, where I and Q paths must be sampled in lockstep to preserve quadrature balance. The JESD204A serial interface allows multiple ADC1613D080HN-C18 parts to be aggregated into a single FPGA, scaling channel count without proportional FPGA pin growth. Differential inputs reject switching noise from the upstream digital baseband block, supporting low bit-error-rate demodulation.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1613D080HN-C18 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1413D080HN-C1 | ADC1413D125HN-C1 | ADC1613D125HN-C18 | ADC1610S125HN-C1 | ADC1112D125HN-C18 |
|---|---|---|---|---|---|---|
| Package | 56-HVQFN (8x8 mm) | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same |
| Brand | Renesas Electronics | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same | Renesas Electronics - same |
| Resolution | 16 bit | 14 bit | 14 bit | 16 bit | 16 bit | 11 bit |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 2 |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Interface | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS | JESD204A LVDS |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
주요 차별점
- Dual-channel simultaneous sampling at full 80 MSPS (vs ADC1610S125HN-C1)
- Higher 16-bit resolution across the same footprint (vs ADC1413D080HN-C1)
- Lower 80 MSPS sample rate vs 125 MSPS family member (vs ADC1613D125HN-C18)
설계 노트
The ADC1613D080HN-C18 requires clean, low-noise analog and digital supplies in the 3.0-3.6 V range. Place a ferrite bead between VDDA and VDDD planes, and decouple each pin with 0.1 uF X7R ceramic in parallel with 10 uF bulk. Use a dedicated LDO upstream (e.g. ADP3339 or TPS7A47xx) to reject switching noise from upstream DC-DC converters; ripple above 10 mVpp on VDDA degrades SFDR by approximately 1-2 dB per octave.
Solder the exposed thermal pad (pin 56) to a continuous ground plane with at least 9 thermal vias (3x3 grid, 0.3 mm drill) for junction-to-board thermal resistance. Maintain a 50-ohm controlled-impedance differential pair layout for CLK+/-, D0+/-, and D1+/- lanes; use length-matched traces within 1 mm to satisfy JESD204A setup/hold. Keep analog input traces short and away from digital output lanes to prevent coupling into the front-end sampling path.
Configure JESD204A link parameters (L, K, M, F) to match the receiving FPGA logic IP core. Mismatched K between the ADC and FPGA causes intermittent frame alignment failures visible as dropped samples. Verify deterministic latency using SYNCIN/SYNCOUT handshaking before enabling downstream processing.
Avoid placing bypass capacitors on REFT and REFB more than 2 mm from their respective pins - long traces introduce series inductance that destabilizes the internal reference loop and causes SFDR roll-off above 30 MHz input. Also ensure the BIAS resistor value matches the manufacturer datasheet (typically 10 kohm 1%); using wrong values shifts the internal bias point and degrades linearity.
규정 준수 정보
RoHS / REACH compliance and lead-free / halogen-free status per Renesas manufacturer datasheet. AEC-Q100 not applicable - this part targets communications and instrumentation, not automotive safety.
