AOZ73004CQI - NVIDIA OpenVReg Multiphase Buck Controller | AOS
N.º de pieza: AOZ73004CQI ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $3.85 | $3,85 |
| 10 | $3.42 | $34,20 |
| 100 | $2.98 | $298,00 |
| 500 | $2.65 | $1.325,00 |
| 1.000 | $2.34 | $2.340,00 |
| 3.000 | $2.05 | $6.150,00 |
AOZ73004CQI Descripción general
What is a multiphase buck controller? In the hierarchy of power management ICs, a buck controller sits above the simple buck converter and below the full PMIC: it is a control IC that drives external power-stage blocks (DrMOS / smart power stages) in parallel to deliver high currents with low ripple. By interleaving the phases (each phase shifted by 360/N degrees), the input and output ripple currents partially cancel, enabling smaller output filter inductors and faster transient response. A PWMVID controller adds a further layer: the output voltage is set point is digitally encoded as a PWM duty cycle, allowing the host (e.g., an NVIDIA GPU) to command DVFS transitions in nanoseconds without I2C or analog VID DAC overhead.
Key features of the AOZ73004CQI include NVIDIA OpenVReg specification compliance, PWMVID interface with external reference input, multi-phase operation (configurable phase count), adaptive voltage positioning for transient load steps, and per-phase current sensing and balancing. The architecture supports N+1 phase redundancy, droop-free operation during dynamic VID transitions, and telemetry outputs (e.g., IMON, TMON, PGOOD) for system-level monitoring.
Typical applications include GPU core power on add-in graphics cards (PCIe x16 form factor), notebook discrete GPU platforms, AI accelerator cards, and desktop CPU VCORE rails. It is also suited to any high-current digital load requiring OpenVReg-compatible DVFS control with low ripple and fast transient response.
When designing the multiphase rail, careful DrMOS selection and inductor sizing are required. The output filter inductance scales inversely with the number of active phases, and the loop compensation network must be tuned to the chosen DrMOS and output capacitance. PWMVID reference integrity is critical - keep the REFIN trace short and shield it from switching noise.
Alternativas directas para AOZ73004CQI — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con AOZ73004CQI (mismo factor de forma y huella) — difiere en Package.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
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Ver hoja de datos →AOZ73004CQI Valores máximos y características eléctricas
| Product Type | Multiphase Buck Controller (PMIC) |
| Number of Output Rails | 1 |
| Compliance Standard | NVIDIA OpenVReg |
| Dynamic Voltage Control Interface | PWMVID with external REFIN input |
| PWMVID Output Voltage Setting | Vmin at 0% duty, Vmax at 100% duty cycle |
| Configuración de salida | Multi-phase buck (DrMOS-based smart power stages) |
| Primary Applications | GPU and CPU core power, graphic cards, desktop and notebook platforms |
| Encapsulado | QFN-32 (5x5 mm) with exposed pad |
| Tipo de montaje | Surface Mount |
| Current Sense Method | Per-phase DCR / IMON (DrMOS interface) |
| Telemetry Outputs | IMON (current monitor), PGOOD (power good) |
| Protection Features | OVP, UVP, OTP (typical for multiphase controllers) |
| Estado RoHS | Compliant |
| Lead-Free Finish | Yes |
Guía de configuración de pines de AOZ73004CQI qfn-32 (5x5 mm) with exposed pad
Configuración de pines para AOZ73004CQI (encapsulado qfn-32 (5x5 mm) with exposed pad). Este dispositivo de potencia presenta terminales de puerta, drenador y fuente. Para encapsulados no polarizados, consulte la hoja de datos del fabricante para conocer la orientación exacta del pin 1 y los detalles del footprint. Las aplicaciones habituales incluyen el diseño de fuentes de alimentación, el accionamiento de motores y la conmutación de cargas.
No hay datos detallados de patillaje disponibles para AOZ73004CQI.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
AOZ73004CQI es adecuado para 6 aplicacións: GPU Core Power (PCIe Add-in Graphics Cards), Notebook Discrete GPU Platform Power, Desktop CPU VCORE Rail, AI Accelerator Card Core Power, Embedded SoC and Multi-Core DSP Power Rails, Server and Datacenter Compute Boards.
GPU Core Power (PCIe Add-in Graphics Cards)
The AOZ73004CQI is purpose-built for GPU core voltage regulation on PCIe add-in graphics cards, which is the headline application called out in the AOS product brief. NVIDIA OpenVReg compliance and a single PWMVID-controlled output rail let the controller track the GPU's per-frame voltage/frequency requests with the nanosecond-class latency demanded by DVFS state transitions. Driving parallel DrMOS stages from one QFN-32 package delivers the 100 A+ core current typical of high-end GPU cards while keeping ripple low via multi-phase interleaving. For drop-in re-use, the same controller can be paired with DrMOS stages such as AOZ5066 or AOZ5076 that share the OpenVReg PWM/IMON interface.
Recomendado
Notebook Discrete GPU Platform Power
Mobile discrete GPU platforms require OpenVReg-compliant DVFS with high efficiency across a wide load range to extend battery life under gaming and content-creation workloads. The AOZ73004CQI's single-rail PWMVID control, plus interleaved DrMOS phases, lets the notebook designer hit both light-load standby efficiency and peak-load transient response from the same controller footprint. The QFN-32 (5x5 mm) exposed-pad package keeps the controller footprint under the GPU VCORE inductor area, simplifying PCB layout where board height is constrained by the chassis profile.
Recomendado
Desktop CPU VCORE Rail
The same OpenVReg DVFS behaviour that the AOZ73004CQI provides for GPUs is also applicable to high-current desktop CPU VCORE rails, where legacy VRM interfaces are being supplemented by PWMVID-based protocols on modern desktop-class CPUs. Used as a VCORE controller driving 4- to 8-phase DrMOS stages, the AOZ73004CQI lets the system designer reuse the GPU power-stage bill of materials on the CPU side. Phase count, switching frequency, and current-sense scaling parameters must be confirmed from the AOS datasheet to match the chosen CPU load line.
Recomendado
AI Accelerator Card Core Power
AI training and inference accelerator cards depend on tight voltage regulation on the GPU/ASIC core to maintain sustained boost clocks across heavy matrix workloads without thermal throttling. The AOZ73004CQI's per-phase current monitoring and adaptive voltage positioning help the regulator respond to millisecond-scale bursts (typical of transformer attention layers) with minimal output voltage droop. Designers of these cards benefit from the controller's pair-and-share capability: PWMVID-based output tracking pairs naturally with the accelerator's internal power-management firmware.
Recomendado
Embedded SoC and Multi-Core DSP Power Rails
Beyond graphics cards, the AOZ73004CQI can drive high-current rails for embedded SoCs and multi-core DSP compute platforms, where OpenVReg-style dynamic voltage scaling is used to manage thermal envelopes in fanless industrial designs. The controller's QFN-32 exposed-pad package dissipates gate-driver losses efficiently, freeing board area for downstream filter components. Stability validation against the chosen DrMOS' loop response and the SoC's transient current step profile is required before locking in the BOM.
Recomendado
Server and Datacenter Compute Boards
Datacenter accelerator modules and CPU server boards requiring OpenVReg DVFS control can adopt the AOZ73004CQI as the rail controller, especially in Open Compute Project (OCP) reference designs where NVIDIA OpenVReg is a common requirement. The controller's telemetry outputs (IMON, PGOOD) plug into BMC-managed telemetry rails for power-capping and efficiency reporting. Check thermal budgets and parallel-phase current sharing against the OCP-class GPU or accelerator's worst-case load line.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para AOZ73004CQI — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | AOZ73004QI | RT9742BGCP | ISL62 8x series | NCP81236 | RT9161-33PX |
|---|---|---|---|---|---|---|
| Brand | Alpha & Omega Semiconductor | Alpha & Omega Semiconductor | Richtek | Renesas Electronics | onsemi | Richtek |
| Package | QFN-32 (5x5 mm) with exposed pad | QFN-32 | QFN-32 | QFN-32 | QFN-32 | QFN-32 |
| Compliance Standard | NVIDIA OpenVReg | NVIDIA OpenVReg | OpenVReg / PWMVID | OpenVReg / VRM | NVIDIA OpenVReg | OpenVReg family |
| Number of Output Rails | 1 | 1 | 1 | 1 | 1 | 1 |
| Dynamic Voltage Interface | PWMVID with external REFIN | PWMVID (verify REFIN) | PWMVID | PWMVID / 8V/VID | PWMVID | PWMVID |
| Multi-Phase Control | Yes (DrMOS stages) | Yes | Yes | Yes | Yes | Yes |
| Telemetry Outputs | IMON, PGOOD | IMON, PGOOD | IMON, PGOOD | IMON, PGOOD, VRHOT | IMON, PGOOD, VRHOT | IMON, PGOOD |
Diferenciadores clave
- NVIDIA OpenVReg compliance with explicit PWMVID REFIN (frente a NCP81236)
Notas de diseño
The AOZ73004CQI's QFN-32 (5x5 mm) exposed pad must be soldered to a continuous copper island with thermal vias for heat extraction into inner PCB copper layers. Estimated: at 4-phase 600 kHz switching with 100 A output at VIN=12V to VOUT=1V, total DrMOS stage dissipation is on the order of 12 W; controller-side gate drive losses are tens of milliwatts and the QFN package handles this easily. For higher phase counts, the controller thermal budget can climb; confirm with the AOS datasheet theta_JA figure before finalizing PCB layout.
Route the BOOT, UGATE, LGATE, and PHASE traces to each DrMOS stage as short and wide as possible (target <25 mm matched-length per phase to balance propagation delay). Place REFIN and its PWMVID input trace away from switching PHASE/UGATE/LGATE nodes and shield with GND on both sides. The exposed pad of the QFN must be placed on top-layer copper with at least 4 thermal vias (0.3 mm drill, 0.5 mm pitch) to inner GND plane. Estimated: failure to follow these trace-length rules increases ringing on PHASE nodes by 2-3x and can cause DrMOS shoot-through.
Input capacitors must be placed as close as possible to each DrMOS stage's VIN/PGND pin pair; ceramic X7R/X5R in 22-47 uF/0805 or 1210 sizes are typical. The output inductor and output capacitor footprint must match the per-phase current rating; verify inductor saturation current exceeds the per-phase peak (typically 30-40% above the per-phase average). The IMON output must return to a quiet analog ground reference; do not share IMON trace with switching return paths.
Do not assume the AOZ73004CQI's pinout matches the AOZ73004QI variant without verification - differ between suffix revisions is possible. Estimated: PGND and AGND pin separation should be preserved on the PCB star-ground topology; do not bridge them under the package. When transferring a design from a non-OpenVReg VRM, REFIN/Vmin/Vmax relationships must be re-derived from the AOS datasheet section on PWMVID interface.
Información de cumplimiento
RoHS compliance inferred from active distributor listings (DigiKey) and lead-free QFN-32 packaging per the AOS product brief. REACH, halogen-free, and conflict-minerals status not explicitly published on the AOS product brief - request the full manufacturer declaration for EU projects requiring REACH SVHC reporting.
