BCM56990B0KFLGG - 25.6Tb/s Ethernet Switch | Broadcom
N.º de pieza: BCM56990B0KFLGG ✓ Activo| Cant. | Precio unitario | Total |
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BCM56990B0KFLGG Descripción general
A multilayer Ethernet switch IC is a networking silicon device that forwards Layer 2 and Layer 3 packets at line rate, integrating MACs, SERDES, packet processors, and a host CPU interface into a single chip. Within the system hierarchy, the switch IC sits at the core of a switch platform, above PHYs and below system software such as a network operating system (NOS).
Key features of the BCM56990 include its 25.6-Tb/s switching capacity, which supports configurations such as 64 ports of 400GbE or high-count 100G/50G breakout modes; the related BCM56990 family member doubles the number of 50G ports from 32 to 64 and introduces 400GbE breakout support. The device integrates a PCIe Gen3 host interface that conforms to the PCIe Gen3 specification and also supports Gen1 and Gen2 operation at x1, x2, or x4 link widths, delivering up to 8.0 GT/s link speed (7.88 Gb/s data rate in each direction) for in-band or out-of-band host management connectivity.
Technically, the BCM56990 implements deep packet-buffering and multilayer forwarding architectures typical of Broadcom's StrataXGS switch families, enabling dense leaf/spine topologies, top-of-rack switching, and high-scale aggregation. The 8371-terminal LGA package requires a high-layer-count PCB with dense via-in-pad design and carefully engineered power delivery.
Typical applications include hyperscale data center switches, enterprise aggregation switches, white-box switch platforms, and storage networking appliances where 100G/400G port density and full multilayer (L2/L3) forwarding are required.
Design consideration: the higher-speed family variants require a higher-performance power delivery network and a faster reference clock (156.25 MHz versus 125 MHz), so clock tree and PDN design must be confirmed against the specific ordering part number before layout reuse.
This page synthesizes distributor availability, cross-reference guidance, and practical design notes not found in the manufacturer datasheet, providing engineers with a single citation-ready reference for the BCM56990B0KFLGG.
Alternativas directas para BCM56990B0KFLGG — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con BCM56990B0KFLGG (mismo factor de forma y huella) — difiere en Mounting Type, Package Type, Product Family.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
BCM56991B0KFLGG
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
BCM56990B0KFLGLG
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
BCM56990B0KFLG
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
BCM56990B0KFLGG Valores máximos y características eléctricas
| Switching Capacity | 25.6 Tb/s |
| Product Family | BCM56990 multilayer switch |
| Device Type | 25.6-Tb/s Multilayer Ethernet Switch |
| Host Interface | PCIe Gen3 (conforms to PCIe Gen3 specification) |
| PCIe Compatibility | Gen1, Gen2, Gen3 |
| PCIe Link Widths | x1, x2, x4 |
| PCIe Link Speed | 8.0 GT/s (7.88 Gb/s data rate per direction) |
| Package Type | LGA (land grid array) |
| Number of Terminals | 8371 |
| Package Shape | Rectangular |
| Package Style | Grid array |
| Terminal Form | No lead |
| Tipo de montaje | Surface Mount |
| Manufacturer | Broadcom Limited |
| Maximum Ports | Up to 64 x 400GbE (family capability) |
Guía de configuración de pines de BCM56990B0KFLGG grid array
Configuración de pines para BCM56990B0KFLGG (encapsulado grid array). Este componente analógico presenta pines de entrada, salida y alimentación. Consulte la hoja de datos del fabricante para conocer las configuraciones de los pines de ajuste de offset, compensación y habilitación. Ideal para circuitos de acondicionamiento de señal y amplificadores.
No hay datos detallados de patillaje disponibles para BCM56990B0KFLGG.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
BCM56990B0KFLGG es adecuado para 6 aplicacións: Hyperscale Data Center Leaf Switch, Top-of-Rack (ToR) 100G Switch, Enterprise Aggregation Switch, White-Box Switch Platform / ODM Design, Storage Networking / SAN Switch, Spine Switch for Leaf-Spine Fabrics.
Hyperscale Data Center Leaf Switch
The BCM56990B0KFLGG fits hyperscale leaf switch platforms because its 25.6-Tb/s switching capacity provides enough bandwidth for 64 x 400GbE or dense 100G breakout configurations in a single die, reducing chip count and simplifying platform BOM. In a typical leaf switch, the device terminates all server-facing and spine-facing SerDes lanes and performs full Layer 2/Layer 3 forwarding at line rate, while the PCIe Gen3 x4 host interface (7.88 Gb/s per direction) connects the management CPU running the network operating system. Because the family supports 400GbE breakout modes, operators can flexibly partition ports between 400G spine uplinks and 25G/50G server downlinks. The trade-off is a demanding 8371-terminal LGA land pattern and enhanced power delivery network, so the platform PCB must be designed for the device from the start.
Recomendado
Top-of-Rack (ToR) 100G Switch
For top-of-rack switching, the BCM56990B0KFLGG delivers the port density needed to aggregate dozens of servers on 25G/50G links while providing 100G and 400G uplinks, all within a single switch fabric device. Its multilayer forwarding supports both L2 bridging within the rack and L3 routing toward the spine, removing the need for external router silicon. The PCIe Gen3 interface, conforming to PCIe Gen3 with Gen1/Gen2 backward compatibility at x1/x2/x4 widths, attaches the BMC or host CPU for out-of-band management without a separate management Ethernet switch. Engineers should budget for the 156.25 MHz reference clock required by the higher-speed family configurations and place clock circuitry close to the device. Buffering and QoS resources on the die allow burst absorption typical of ToR traffic patterns.
Recomendado
Enterprise Aggregation Switch
In enterprise campus aggregation, the BCM56990B0KFLGG provides 25.6 Tb/s of non-blocking multilayer switching capacity to aggregate multiple access switches over 100G fiber links, with headroom for 400G upgrade paths enabled by the family's 400GbE breakout support. The device's L2/L3 feature set handles VLANs, routing, and QoS policies centrally, and the PCIe Gen3 host interface supports the control processor running enterprise network OS software. Compared with stacking multiple lower-capacity switch ICs, a single BCM56990-based aggregation platform lowers power per gigabit and simplifies software bring-up within the Broadcom StrataXGS software ecosystem. Platform designers must account for the 8371-terminal LGA assembly requirements and the enhanced power delivery network noted for this device generation.
Recomendado
White-Box Switch Platform / ODM Design
White-box and ODM switch platforms favor the BCM56990B0KFLGG because Broadcom StrataXGS switch silicon is supported by the majority of open network operating systems, letting ODMs reuse SDK integrations across generations. The 25.6-Tb/s capacity maps directly to common white-box configurations such as 64-port 400G or mixed 100G/50G breakout systems. The PCIe Gen3 x4 management interface (8.0 GT/s, 7.88 Gb/s per direction) is the standard attachment for the commodity x86 management CPU in these platforms. When migrating an existing ODM design from a prior family member, note that the BCM56990 requires a faster 156.25 MHz reference clock (versus 125 MHz) and a higher-performance power delivery network, so both the clock tree and PDN must be re-verified rather than copy-reused.
Recomendado
Storage Networking / SAN Switch
Storage area network switches benefit from the BCM56990B0KFLGG's deterministic line-rate multilayer forwarding and its 25.6-Tb/s capacity, which sustains dense 100G/400G ISL (inter-switch link) topologies between storage arrays and compute racks. Low-latency packet processing within the switch fabric helps meet the strict latency budgets of block-storage protocols carried over Ethernet fabrics. The PCIe Gen3 host interface provides a reliable control-plane path to the fabric management processor, supporting Gen1 through Gen3 for backward-compatible platform designs. Because storage platforms demand long field lifetimes, designers should qualify a same-family second source, such as the BCM56991 variant, during initial design to mitigate supply risk, while confirming identical land pattern and clock requirements from the Broadcom documentation.
Recomendado
Spine Switch for Leaf-Spine Fabrics
As a spine switch fabric, the BCM56990B0KFLGG concentrates uplinks from multiple leaf switches, where its 25.6-Tb/s capacity and 400GbE breakout support allow high-radix connectivity using fewer 400G lanes and breakout cables. Full Layer 3 forwarding at every spine port enables ECMP load balancing across the fabric without external routing silicon. The device's deep buffering absorbs incast bursts common in distributed storage and AI traffic patterns. Integration effort centers on the 8371-terminal LGA PCB breakout and the enhanced power delivery network required by this generation; Broadcom reference designs for the BCM56990 series should be followed for decoupling and layer stackup. The PCIe Gen3 management interface attaches the fabric controller in the standard x4 configuration.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para BCM56990B0KFLGG — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | BCM56991B0KFLGG | BCM56990B0KFLGLG | BCM56990B0KFLG |
|---|---|---|---|---|
| Package | LGA-8371 (rectangular grid array, no lead) | LGA-8371 - same | LGA-8371 - same | LGA-8371 - same |
| Brand | Broadcom | Broadcom | Broadcom | Broadcom |
| Switching Capacity | 25.6 Tb/s | 25.6 Tb/s (higher-speed SKU) | 25.6 Tb/s | 25.6 Tb/s |
| Host Interface | PCIe Gen3 (Gen1/Gen2 compatible), x1/x2/x4 | PCIe Gen3 (Gen1/Gen2 compatible), x1/x2/x4 | PCIe Gen3 (Gen1/Gen2 compatible), x1/x2/x4 | PCIe Gen3 (Gen1/Gen2 compatible), x1/x2/x4 |
| Number of Terminals | 8371 | 8371 | 8371 | 8371 |
| 400GbE Breakout Support | Yes (family capability) | Yes | Yes (family) | Yes (family) |
| Price Tier (qty 1) | RFQ - not published | RFQ - not published | RFQ - not published | RFQ - not published |
Diferenciadores clave
- Doubled 50G port count (frente a Prior BCM569xx family members)
- Native PCIe Gen3 host interface (frente a Switch ICs requiring external management MAC/FPGA)
- Trade-off: stricter platform requirements (frente a Earlier BCM569xx parts)
Notas de diseño
The BCM56990 family requires a higher-performance power delivery network than prior generations, per distributor product information (IC-Components). With a 25.6-Tb/s SerDes fabric, core rail transient currents are large; design multi-phase VRM stages with bulk capacitance at the LGA die side and verify the power rail map against the Broadcom NDA datasheet before finalizing the PCB power plane stackup. Do not reuse the PDN from earlier BCM569xx generations without re-simulation, since rail count and current profiles differ.
The reference clock requirement changes across the family: the higher-performance variant uses 156.25 MHz versus 125 MHz on earlier parts. Confirm the required frequency for the exact orderable suffix before laying out the clock tree, and keep the clock source close to the device with a low-jitter (high-performance) oscillator suitable for multi-hundred-gigabit SerDes reference inputs. Clock jitter directly impacts the 25G/50G/100G SerDes bit-error performance on all 400GbE breakout lanes.
The 8371-terminal LGA package demands a high-layer-count PCB with via-in-pad breakout under the device. Follow Broadcom's package qualification and land pattern documentation for pad geometry and coplanarity-driven stencil design. Plan escape routing with at least one dedicated layer group for the PCIe Gen3 x4 management links (8.0 GT/s) and maintain controlled impedance per the PCIe Gen3 specification the interface conforms to. Recommend full signal-integrity simulation of the SerDes escape region prior to first spin.
A common migration error is assuming cross-family pin or clock compatibility: although the BCM56990 shares footprint characteristics with same-family variants, the clock (156.25 MHz vs 125 MHz) and PDN requirements changed in this generation. Always design to the full orderable part number BCM56990B0KFLGG, and re-verify land pattern, clock, and power tree when substituting any suffix variant. Broadcom gates the full datasheet behind NDA - obtain it before layout freeze.
Información de cumplimiento
Compliance data not published in the retrieved web sources; Broadcom product compliance documents should be requested from the manufacturer or distributor.
