BCM56992B0KFLGG - 25.6Tb/s 400GbE Switch IC | Broadcom
N.º de pieza: BCM56992B0KFLGG ✓ Activo| Cant. | Precio unitario | Total |
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| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
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| 500 | $0 | $0,00 |
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BCM56992B0KFLGG Descripción general
An Ethernet switch fabric IC is the core forwarding engine of a network switch: it terminates high-speed SerDes lanes from optical modules or copper PHYs, buffers packets in deep on-chip memory, and performs lookup, classification, and rewrite operations at line rate. In the network hierarchy, it sits above PHY and retimer devices and below the host CPU and software stack (e.g., SONiC, Linux switchdev), forming the packet-processing heart of data center switching platforms.
Key features include 64x400GbE or 128x200GbE port configurations, 25.6 Tb/s aggregate bandwidth, 50G PAM4 SerDes lanes for direct connection to 400G DR4/FR4 optics, hardware L2 learning, L3 routing (IPv4/IPv6), ACLs, ECMP, VXLAN overlay support, and advanced telemetry for congestion and latency monitoring. The Tomahawk 4 generation targets hyperscale cloud and AI/ML cluster fabrics where radix and bandwidth density are decisive.
Architecturally, the BCM56992B0KFLGG belongs to Broadcom's StrataXGS family, known for scalability, flexibility, and advanced feature integration. The 50G PAM4 SerDes interface doubles lane bandwidth over NRZ 25G designs, allowing 400GbE ports on 8 lanes and reducing PCB layer count and connector cost. Shared packet buffer memory and programmable pipeline stages enable flexible protocol handling without external co-processors.
Typical applications include top-of-rack (ToR) and spine switches for hyperscale data centers, AI/ML training cluster leaf-spine fabrics, enterprise core switching platforms, and white-box switch designs running NOS software such as SONiC. High radix and 400GbE density make it well matched to 400G uplink aggregation.
Design considerations center on thermal and signal integrity: the FCBGA package requires a carefully engineered heatsink, high-layer-count PCB, and disciplined 50G PAM4 breakout routing. Verify SerDes reach and PCB stackup against Broadcom reference designs before layout release.
This page synthesizes distributor availability data, Tomahawk 4 architecture context, and practical design guidance not found in a single datasheet, helping engineers evaluate the BCM56992B0KFLGG against family variants for 400GbE switch designs.
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Solicitar alternativasBCM56992B0KFLGG Valores máximos y características eléctricas
| Product Family | StrataXGS Tomahawk 4 |
| Switching Capacity | 25.6 Tb/s |
| Max Port Configuration | 64 x 400GbE |
| Alternative Port Configurations | 128 x 200GbE, 256 x 100GbE |
| SerDes Technology | 50G PAM4 |
| Forwarding Layers | L2 / L3 multilayer (IPv4/IPv6) |
| Package Type | FCBGA |
| Overlay Support | VXLAN / NVGRE tunneling |
| Telemetry | Hardware congestion and latency telemetry |
| Target Applications | Data center, enterprise networking, AI/ML cluster fabrics |
| Tipo de montaje | Surface Mount (BGA) |
Guía de configuración de pines de BCM56992B0KFLGG fcbga
Configuración de pines para BCM56992B0KFLGG (encapsulado fcbga). Este componente analógico presenta pines de entrada, salida y alimentación. Consulte la hoja de datos del fabricante para conocer las configuraciones de los pines de ajuste de offset, compensación y habilitación. Ideal para circuitos de acondicionamiento de señal y amplificadores.
No hay datos detallados de patillaje disponibles para BCM56992B0KFLGG.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
BCM56992B0KFLGG es adecuado para 6 aplicacións: Hyperscale Data Center Spine Switch, AI/ML Training Cluster Leaf-Spine Fabric, Enterprise Core and Aggregation Switching, White-Box Switch Platform (SONiC), 400G Data Center Interconnect (DCI) Gateway, Test and Measurement / Fabric Validation Systems.
Hyperscale Data Center Spine Switch
The BCM56992B0KFLGG fits spine switching because 25.6 Tb/s and 64 x 400GbE provide the radix needed to interconnect dozens of leaf switches without oversubscription. Its 50G PAM4 SerDes connects directly to 400G DR4/FR4 optics, removing external PHYs and lowering system cost, while hardware ECMP spreads traffic across parallel leaf paths at line rate. In a spine role, the device performs L3 routing for the fabric underlay and VXLAN gateway functions where overlays terminate. Performance consideration: spine configurations exercise nearly all SerDes lanes simultaneously, so PCB stackup, connector selection, and airflow must follow the Broadcom reference design to hold PAM4 link margin and keep junction temperature within spec at full 25.6 Tb/s utilization.
Recomendado
AI/ML Training Cluster Leaf-Spine Fabric
AI/ML training jobs generate massive east-west all-reduce traffic, and the BCM56992B0KFLGG addresses this with 64 x 400GbE ports, deep buffering, and hardware congestion telemetry that feeds adaptive routing in the NOS. Third-party technical guides (aichiplink, Dec 2025) specifically identify this Tomahawk 4 device as an engine for 400GbE AI cluster designs with SONiC integration. In leaf roles, each port typically terminates a 400G optic to a GPU server group or spine; ECMP and telemetry-driven load balancing keep long-lived RDMA/NCCL flows from hot-spotting links. Design consideration: lossless behavior depends on end-to-end priority flow control and ECN configuration in the pipeline, so fabric QoS tuning is as important as raw bandwidth when sizing the cluster's bisection bandwidth.
Recomendado
Enterprise Core and Aggregation Switching
Enterprise campus cores need high-radix 100G/400G aggregation with full L3 feature depth, which the BCM56992B0KFLGG provides through hardware IPv4/IPv6 routing, ACLs, VXLAN overlay termination for SD-Access fabrics, and MPLS-ready StrataXGS pipeline features. The 25.6 Tb/s capacity supports collapsed core designs serving many wiring closets without oversubscription, and 50G PAM4 SerDes allows cost-effective 400G uplinks over campus-qualified optics. Unlike data-center-only devices, the StrataXGS software ecosystem supplies the mature feature set enterprise platforms require. Performance consideration: enterprise deployments value power efficiency at partial utilization, so platform vendors should validate power and thermals at realistic traffic loads, not only worst case, when sizing chassis airflow and power supplies.
Recomendado
White-Box Switch Platform (SONiC)
White-box and brite-box switch vendors build ODM platforms around the BCM56992B0KFLGG because Broadcom supplies SAI-compatible SDK support enabling SONiC and other open NOS stacks. The 64 x 400GbE port map matches common ODM 64x400G board designs, and hardware telemetry exposes queue and latency counters that SONiC's telemetry framework consumes directly. For hyperscalers, this decouples hardware procurement from NOS licensing and enables rapid software iteration. Performance consideration: platform qualification is tied to a specific Broadcom SDK branch and SONiC release, not the silicon alone, so white-box teams must lock an SDK/SONiC version pair early in the program and verify device ID support before board bring-up to avoid firmware compatibility surprises late in development.
Recomendado
400G Data Center Interconnect (DCI) Gateway
At the data center edge, the BCM56992B0KFLGG serves as a high-capacity gateway that aggregates east-west traffic and hands off to 400G ZR/ZR+ coherent DCI optics. Its 25.6 Tb/s fabric absorbs bursty inter-site replication and backup traffic, while VXLAN termination lets overlay tenants extend across sites transparently. ACL and telemetry hardware supports tenant isolation and flow-level performance monitoring at the handoff point. In this role only a subset of SerDes lanes drives the DCI uplinks, leaving headroom for future bandwidth growth without a forklift upgrade. Design consideration: validate the SerDes channel budget from switch ball through the board and module cage for the specific 400G optic type, since PAM4 margin is the dominant risk in DCI gateway layouts.
Recomendado
Test and Measurement / Fabric Validation Systems
Network test equipment makers use the BCM56992B0KFLGG as a packet generation and capture fabric because 64 x 400GbE ports and deterministic hardware forwarding allow dense traffic generation, latency measurement, and capture aggregation in a single chassis. The programmable StrataXGS pipeline supports custom frame manipulation, checksum offload, and timestamping suitable for RFC 2544/2889-style benchmarking at 400G rates, which would otherwise require many discrete test appliances. Hardware telemetry gives test software per-queue visibility during congestion testing. Performance consideration: measurement systems must account for the device's fixed pipeline latency and any cut-through/store-and-forward mode differences, calibrating results against a known reference so reported latency figures isolate the device under test rather than the switch fabric itself.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para BCM56992B0KFLGG — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | BCM56990B0KFLGG | BCM56991B0KFLGG | BCM56994B0KFLGG |
|---|---|---|---|---|
| Brand | Broadcom | Broadcom | Broadcom | Broadcom |
| Package | FCBGA | FCBGA | FCBGA | FCBGA |
| Switching Capacity | 25.6 Tb/s | 12.8 Tb/s | 12.8 Tb/s | 25.6 Tb/s |
| Max 400GbE Ports | 64 | 32 | 32 | 64 |
| SerDes Technology | 50G PAM4 | 50G PAM4 | 50G PAM4 | 50G PAM4 |
| Forwarding Layers | L2/L3 multilayer | L2/L3 multilayer | L2/L3 multilayer | L2/L3 multilayer |
| Product Generation | Tomahawk 4 | Tomahawk 4 | Tomahawk 4 | Tomahawk 4 |
Diferenciadores clave
- Double the bandwidth density of 12.8T Tomahawk 4 siblings (frente a BCM56990B0KFLGG)
- Full-flagship capacity within Tomahawk 4 generation (frente a BCM56994B0KFLGG)
- 50G PAM4 SerDes halves lane count versus 25G NRZ designs (frente a BCM56990B0KFLGG)
Notas de diseño
Estimated: a 25.6 Tb/s switch fabric of this class dissipates tens of watts depending on configuration; since the exact figure is not in the provided data, obtain it from the official Broadcom thermal design guide before sizing cooling. Plan a dedicated heatsink with thermal interface material and forced airflow per the Broadcom platform reference design. Do not rely on PCB copper alone - data-center switch silicon always requires a chassis fan curve validated against worst-case traffic. Verify junction temperature targets at maximum SerDes lane utilization (all 64 ports at 400G) rather than at partial load.
50G PAM4 signaling provides roughly 9 dB less signal-to-noise margin than 25G NRZ, making channel engineering the dominant PCB risk. Use low-loss laminate, minimize via stubs (back-drill or blind/buried vias), keep host-side breakouts within Broadcom's reference reach, and choose module cages and connectors rated for 50G PAM4. Simulate each SerDes channel's insertion loss and return loss against the Broadcom channel compliance mask before layout release, and perform compliance testing with the vendor's SerDes tuning tools during bring-up.
Do not assume family interchangeability: BCM56990/91/94 and BCM56992 have different device IDs, ball maps, and firmware images, so a board designed for one cannot simply accept another. Lock the Broadcom SDK and NOS (e.g., SONiC) version pair at program start, since device support is tied to the SDK branch. Also confirm the exact power, thermal, and buffer specifications from the official NDA datasheet rather than aggregator summaries, which may describe related family members instead of the BCM56992B0KFLGG itself.
Información de cumplimiento
Compliance data not present in the provided web data. Broadcom data-center devices are typically RoHS-compliant, but this must be confirmed via the official Broadcom product compliance page before use.
