CD4017BEE4 - CMOS Decade Counter/Divider, 10MHz, 16-PDIP | TI
N.º de pieza: CD4017BEE4 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $0.58 | $0,58 |
| 10 | $0.51 | $5,10 |
| 100 | $0.42 | $42,00 |
| 500 | $0.36 | $180,00 |
| 1.000 | $0.31 | $310,00 |
CD4017BEE4 Descripción general
A decade counter is a sequential logic device that advances through ten unique states per clock cycle, then automatically resets. The CD4017 belongs to the CD4000 series of CMOS logic ICs, sitting in the broader family of logic ICs, digital ICs, and ultimately semiconductors. This counter is widely used to convert a clock pulse train into a one-of-N sequential output, eliminating the need for a decoder circuit in many designs.
Key features include five Johnson-counter stages with decoded 1-of-10 active-high outputs, an active-low carry-out for cascading multiple counters, a low clock-pulse count of ten per cycle, and fully static synchronous operation. Symmetrical output characteristics ensure consistent rise and fall times, and the device includes a clock-inhibit control and a master reset for flexible timing applications. Its wide supply range (3 V to 18 V) and CMOS low power make it a versatile general-purpose sequencing element.
Architecturally, the CD4017BEE4 implements five D-type flip-flops arranged as a Johnson counter with built-in decode gating that produces ten mutually-exclusive active-high outputs. Each rising edge of the clock pin increments the internal state and shifts the active-high decode to the next output in sequence. A clock inhibit input disables counting without resetting state, while the master reset asynchronously clears all outputs and returns Q0 high.
Typical applications include LED sequencer chasers, frequency division (divide-by-N), keyboard encoders, and decade counting displays. Its 10 MHz typical clock and 18 V rating also suit industrial control timing, hobby electronics, and educational digital logic training. When designing with the CD4017BEE4, place a 0.1 µF decoupling capacitor close to the VDD pin and a 1 µF to 10 µF bulk capacitor on the supply rail. Tie unused active-high outputs either to known states or through resistors, and observe the clock-inhibit setup time before re-enabling counting to avoid spurious counts. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternativas directas para CD4017BEE4 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con CD4017BEE4 (mismo factor de forma y huella) — difiere en Logic Family, Mounting Type, Operating Temperature, RoHS Status, Trigger Type.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
CD4017BE
✅ Sustitución directa✓ En stock
$0.3 / unidad
Ver hoja de datos →MC14017BCP
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
HEF4017BP,652
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CD4017BCN
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CD4017BEE4 Valores máximos y características eléctricas
| Logic Family | CD4000 (CMOS) |
| Counter Type | Decade Counter / Divider |
| Number of Elements | 1 |
| Number of Bits per Element | 10 |
| Trigger Type | Positive, Negative Edge |
| Supply Voltage (VDD) | 3 V to 18 V |
| Typical Clock Frequency @ VDD=10V | 10 MHz (typ) |
| Quiescent Current Test | 100% tested at 20 V |
| Parametric Ratings | 5 V, 10 V, 15 V |
| Configuración de salida | Decoded 1-of-10 active-high |
| Carry Output | Active-low carry-out (CO) |
| Master Reset | Yes (active-high) |
| Clock Inhibit | Yes |
| Temperatura de funcionamiento | -55 C to +125 C |
| Encapsulado / Carcasa | 16-DIP (0.300 inch, 7.62 mm) |
| Tipo de montaje | Through Hole |
| Standard | JEDEC Tentative Standard No. 13-A |
| Estado RoHS | Compliant |
Configuración de pines de CD4017BEE4
| Pin 1 | Q5 — Decoded output 5 (active high) |
| Pin 2 | Q1 — Decoded output 1 (active high) |
| Pin 3 | Q0 — Decoded output 0 (active high, also power-on default) |
| Pin 4 | Q2 — Decoded output 2 (active high) |
| Pin 5 | Q6 — Decoded output 6 (active high) |
| Pin 6 | Q7 — Decoded output 7 (active high) |
| Pin 7 | Q3 — Decoded output 3 (active high) |
| Pin 8 | VSS — Ground |
| Pin 9 | Q8 — Decoded output 8 (active high) |
| Pin 10 | Q4 — Decoded output 4 (active high) |
| Pin 11 | Q9 — Decoded output 9 (active high) |
| Pin 12 | CO — Carry-out (active-low, completes one cycle when Q9 finishes) |
| Pin 13 | CK INH — Clock inhibit (active-high disables counting) |
| Pin 14 | CLK — Clock input (rising edge triggered) |
| Pin 15 | RESET — Master reset (active-high clears to Q0) |
| Pin 16 | VDD — Positive supply (3 V to 18 V) |
Aplicaciones típicas
CD4017BEE4 es adecuado para 6 aplicacións: LED Chaser / Sequencer, Frequency Divider (Divide-by-N), Keyboard / Matrix Encoder, Decade Counting Display, Industrial Control Sequencing, Hobby / Educational Digital Logic.
LED Chaser / Sequencer
The CD4017BEE4's decoded 1-of-10 outputs make it ideal for driving ten LEDs in sequence from a single clock source. With its 10 MHz typical clock and 3 V to 18 V supply, the part can be clocked by a 555 timer or oscillator to produce chase, marquee, or knight-rider patterns at any speed. The active-low carry-out pin allows cascading a second CD4017 for 20-step patterns without extra glue logic. Place a current-limit resistor on each output and tie unused outputs to GND to minimize switching noise.
Recomendado
Frequency Divider (Divide-by-N)
The CD4017BEE4 can divide an input clock by any integer from 1 to 10 using the clock-inhibit pin and decoded outputs as feedback to the reset. This makes it suitable for generating sub-harmonics of a master clock, deriving baud-rate clocks from higher-frequency oscillators, or building prescalers for frequency counters. With a 10 MHz typical clock rating at VDD = 10 V, the part handles most audio and low-RF baseband frequencies. Each decoded output changes state synchronously, avoiding glitches typical of ripple counters.
Recomendado
Keyboard / Matrix Encoder
The CD4017BEE4 can scan a 10-key matrix by sequencing one of ten decoded outputs as a row driver while reading column inputs. Its 5 V / 10 V / 15 V parametric ratings allow direct interface to TTL, CMOS, or mixed logic families without level shifters. The clock-inhibit pin lets the microcontroller pause scanning during debounce or interrupt handling. Power consumption remains low because of CMOS quiescent currents, making the part suitable for battery-powered keyboards and human-interface panels.
Recomendado
Decade Counting Display
Pairing the CD4017BEE4 with a BCD-to-7-segment decoder like the CD4511 and a common-cathode display yields a multi-digit decade counter without a microcontroller. Each pulse clocks the CD4017, which lights the next LED or advances a digit display; the carry-out pin daisy-chains additional stages. With a 3 V to 18 V supply, the same circuit can run from a 9 V battery or a 15 V industrial rail. The master reset allows power-on zeroing through an RC network.
Recomendado
Industrial Control Sequencing
In factory automation and process control, the CD4017BEE4 sequences solenoid valves, motor starters, or indicator lamps through a fixed order driven by a control-system pulse train. Its -55 C to +125 C operating range and JEDEC-13A CMOS compliance suit harsh industrial environments. The wide 3 V to 18 V supply lets it interface directly with 24 V logic through a resistor drop or to 5 V microcontrollers. Built-in clock-inhibit and master reset give operators manual override capability.
Recomendado
Hobby / Educational Digital Logic
The CD4017BEE4 is one of the most widely used CMOS ICs in hobby electronics and STEM education because it produces visible, sequential outputs that make digital logic concepts tangible. It is breadboard-friendly in 16-PDIP, runs from a 9 V battery, and pairs naturally with a 555 timer clock and discrete LEDs. Decoded outputs give students immediate feedback on timing, sequencing, and Johnson-counter topology without microcontrollers. The same datasheet covers CD4017B across TI, onsemi, and NXP second-sources, making lab part substitution straightforward.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para CD4017BEE4 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | CD4017BE | MC14017BCP | HEF4017BP,652 | CD4017BCN |
|---|---|---|---|---|---|
| Package | 16-PDIP (0.300 inch) | 16-PDIP - same | 16-PDIP - same | DIP-16 - same | 16-PDIP - same |
| Brand | Texas Instruments | Texas Instruments | onsemi | NXP Semiconductors | onsemi |
| Logic Family | CD4000 CMOS | CD4000 CMOS | CD4000 CMOS | CD4000 CMOS (HEF) | CD4000 CMOS |
| Supply Voltage | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V |
| Typical Clock Frequency @ VDD=10V | 10 MHz | 10 MHz | 11 MHz | 9 MHz | 10 MHz |
| Number of Decoded Outputs | 10 | 10 | 10 | 10 | 10 |
| Carry-Out | Active-low | Active-low | Active-low | Active-low | Active-low |
| Master Reset / Clock Inhibit | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Diferenciadores clave
- Highest-volume mature CD4017B silicon with E4 bulk packaging (frente a CD4017BE)
- Texas Instruments branded and authorized-channel source (frente a MC14017BCP)
- Wide 3 V to 18 V supply exceeds HEF4017 typical rating (frente a HEF4017BP,652)
Notas de diseño
Decouple the CD4017BEE4 VDD pin (pin 16) with a 0.1 uF ceramic capacitor placed within 5 mm of the package, and add a 1 uF to 10 uF bulk capacitor on the supply rail. Although the CD4000 CMOS family draws low quiescent current, dynamic supply current spikes during output transitions; without local decoupling, these spikes can couple into the clock pin and cause spurious counts. The 100% tested-at-20V quiescent current spec from TI confirms the part is well-behaved at higher rails.
Observe the clock-inhibit setup time before re-enabling counting on pin 13 to avoid spurious counts. The master reset (pin 15) is asynchronous and active-high - tying it through an RC network gives a clean power-on reset to Q0. Unused decoded outputs (Q0-Q9) may be left open if not driven, but floating outputs can pick up noise; tie them to VSS through a 100 kohm resistor if long wires are present. Cascaded counters must wire carry-out (pin 12) of the first stage into clock (pin 14) of the next.
Through-hole 16-PDIP layouts should leave room for a 7.62 mm (0.300 inch) row spacing and standard 2.54 mm pin pitch. Keep clock traces short and away from high-current switching outputs (Q0-Q9, CO) to minimize capacitive crosstalk. If the CD4017BEE4 drives LEDs through resistors, route the LED return currents directly to the same ground node as pin 8 (VSS) to avoid ground bounce that could retrigger the clock input.
Información de cumplimiento
RoHS compliant per TI product folder; E4 suffix denotes bulk packaging. AEC-Q100 not applicable - this is a commercial-grade CMOS logic IC, not an automotive-qualified part.
