CDK1308DILP40 - 10-bit 80MSPS Low-Power ADC | MaxLinear
N.º de pieza: CDK1308DILP40 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $12.5 | $12,50 |
| 10 | $11.25 | $112,50 |
| 100 | $9.85 | $985,00 |
| 500 | $8.5 | $4.250,00 |
| 1.000 | $7.2 | $7.200,00 |
CDK1308DILP40 Descripción general
An ADC is a data-conversion integrated circuit that samples continuous analog signals and translates them into discrete digital codes for downstream microcontrollers, DSPs, or FPGAs. Pipeline ADCs like the CDK1308 family enable high-speed multi-MHz sampling with low power, occupying a middle position between low-speed SAR ADCs and very high-speed flash converters. The CDK1308DILP40 belongs to the broader data-acquisition and signal-chain semiconductor hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor device.
Key features include a 10-bit parallel CMOS output interface, internal reference circuitry (eliminating external reference cost), a single 1.8 V analog supply rail plus a wide 1.7-3.6 V digital I/O supply for flexible host interfacing, and pin compatibility with the lower-speed CDK1307 family (40/65 MSPS) which allows one PCB layout to support multiple sampling-rate SKUs. Its 61.6 dB SNR is competitive for general-purpose imaging and baseband digitisation.
Architecturally the CDK1308DILP40 uses a multi-stage pipeline core with proprietary error-correction logic and on-chip track-and-hold, allowing it to maintain low spurious content across the full Nyquist band without external calibration. The internal voltage reference simplifies design-in and reduces external BOM count.
Typical applications include portable and handheld imaging systems, ultrasound front-end preprocessing, video digitisation, low-cost digital oscilloscopes, and industrial barcode/line-scan cameras where 80 MSPS and 10-bit resolution hit the application sweet spot. The wide 1.7-3.6 V digital I/O supply makes the part especially easy to interface with 1.8 V, 2.5 V, or 3.3 V FPGAs and processors without level shifters.
When designing with this device, pay attention to the analog input common-mode voltage and provide a properly-decoupled analog AVDD rail; place the decoupling capacitors as close to the AVDD and DVDD pins as the layout allows to preserve the 61.6 dB SNR figure.
This page aggregates distributor pricing, drop-in alternatives and practical layout notes - information not bundled together on any single manufacturer or distributor page.
Alternativas directas para CDK1308DILP40 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con CDK1308DILP40 (mismo factor de forma y huella) — difiere en Package, Architecture, Input Type, Reference, Resolution.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
CDK1308CILP40
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$5.7 / unidad
Ver hoja de datos →CDK1307CILP40
✅ Sustitución directa✓ En stock
$3.95 / unidad
Ver hoja de datos →CDK1308DILP40 Valores máximos y características eléctricas
| Resolución | 10 bit |
| Sampling Rate (max) | 80 MSPS |
| Number of Channels | 1 |
| SNR | 61.6 dB at Fin = 8 MHz |
| Power Dissipation | 46 mW |
| Analog Supply Voltage | 1.8 V |
| Digital I/O Supply Voltage | 1.7 V to 3.6 V |
| Output Interface | Parallel CMOS |
| Input Type | Single-ended |
| Reference | Internal |
| Architecture | Pipeline |
| Rango de temperatura de funcionamiento | -40C to +85C |
| Encapsulado | 40-pin QFN (6x6 mm) |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant |
| Pin Compatible With | CDK1307 family |
Configuración de pines de CDK1308DILP40
| Pin 1 | AIN — Analog input |
| Pin 2 | AVSS — Analog ground |
| Pin 3 | AVDD — Analog supply 1.8 V |
| Pin 4 | REFT — Internal reference top (decoupling) |
| Pin 5 | REFB — Internal reference bottom (decoupling) |
| Pin 6 | REFGND — Reference ground |
| Pin 7 | BIAS — Bias reference (decoupling) |
| Pin 8 | PLAVDD — PLL analog supply |
| Pin 9 | PLAVSS — PLL analog ground |
| Pin 10 | PLLDVDD — PLL digital supply |
| Pin 11 | PLLDVSS — PLL digital ground |
| Pin 12 | CLK+ — Differential clock positive input |
| Pin 13 | CLK- — Differential clock negative input |
| Pin 14 | CLKDVDD — Clock digital supply |
| Pin 15 | CLKGND — Clock ground |
| Pin 16 | OE — Output enable (active high) |
| Pin 17 | D9 — Data output bit 9 (MSB) |
| Pin 18 | D8 — Data output bit 8 |
| Pin 19 | D7 — Data output bit 7 |
| Pin 20 | D6 — Data output bit 6 |
| Pin 21 | D5 — Data output bit 5 |
| Pin 22 | D4 — Data output bit 4 |
| Pin 23 | D3 — Data output bit 3 |
| Pin 24 | D2 — Data output bit 2 |
| Pin 25 | D1 — Data output bit 1 |
| Pin 26 | D0 — Data output bit 0 (LSB) |
| Pin 27 | DRVDD — Output driver digital supply |
| Pin 28 | DRVSS — Output driver ground |
| Pin 29 | NC — Not connected |
| Pin 30 | NC — Not connected |
| Pin 31 | PD — Power-down (active high) |
| Pin 32 | RST — Reset / mode select |
| Pin 33 | DVDD — Digital core supply |
| Pin 34 | DVSS — Digital ground |
| Pin 35 | SDOUT — Serial data output (test mode) |
| Pin 36 | SDIO — Serial data I/O (test mode) |
| Pin 37 | SCLK — Serial clock (test mode) |
| Pin 38 | SEN — Serial port enable (test mode) |
| Pin 39 | CAL — Calibration pin |
| Pin 40 | EP — Exposed pad - thermal/ground connection |
Aplicaciones típicas
CDK1308DILP40 es adecuado para 6 aplicacións: Portable Handheld Imaging Systems, Medical Ultrasound Front-End Digitisation, Video Digitisation and Broadcast Capture, Digital Oscilloscope and Test Instrumentation, Industrial Line-Scan and Machine Vision Cameras, Communications Baseband Digitisation.
Portable Handheld Imaging Systems
The CDK1308DILP40 fits handheld cameras, digital still cameras, machine-vision cameras and portable medical-imaging capture boards where 10-bit resolution at 80 MSPS is sufficient and every milliwatt of power matters. The 46 mW typical dissipation at 80 MSPS lets the ADC sit on a single 1.8 V analog rail driven directly from a Li-ion boost converter without a separate LDO, reducing the BOM. The 1.7-3.6 V DVDD also lets the parallel CMOS output drive 1.8 V or 2.5 V image processors without level shifters, simplifying PCB routing and shrinking the capture chain. Compared with a typical 10-bit 80 MSPS competitor, the CDK1308DILP40's internal voltage reference further reduces external component count, which is a critical advantage for compact camera form factors.
Recomendado
Medical Ultrasound Front-End Digitisation
The CDK1308DILP40 targets low-end ultrasound receive-channel digitisation where each channel needs 10-bit resolution at up to 80 MSPS and minimal power to keep probe heat down. With 46 mW dissipation per channel, the ADC enables multi-channel probe-array designs (8-16 channels) that stay within medical-device thermal budgets. The 61.6 dB SNR at 8 MHz input is sufficient for general-purpose B-mode imaging and supports the high-input-frequency content typical of ultrasonic receive signals. The 40-pin QFN (6x6 mm) footprint is also compact enough to fit into phased-array probe pitch constraints. For higher-tier ultrasound requiring 12-14 bit resolution designers should step up to AD927x-family ADCs from Analog Devices, but for cost-optimised handheld probes the CDK1308DILP40 hits the sweet spot.
Recomendado
Video Digitisation and Broadcast Capture
The CDK1308DILP40 is well-matched to standard-definition and progressive-scan video digitisation, professional video capture cards, and security/DVR recording subsystems. At 80 MSPS with 10-bit resolution it comfortably over-samples 27 MHz SDI and 74.25 MHz HD-SDI component streams, providing the digitisation headroom needed for broadcast-grade capture cards while consuming only 46 mW. The parallel CMOS output keeps latency low - critical for live monitoring, waveform display, and time-sensitive broadcast routing applications where analog-to-digital conversion delay must remain minimal. The wide 1.7-3.6 V digital I/O supply supports direct connection to FPGA-based frame-grabbers and ASIC video processors, eliminating level-shift circuitry on the parallel output bus and enabling dense multi-channel layouts on a single capture board.
Recomendado
Digital Oscilloscope and Test Instrumentation
The CDK1308DILP40 fits low-cost 100-200 MHz class digital-storage oscilloscopes, data-acquisition front-ends, and educational/embedded-test instruments where 80 MSPS 10-bit digitisation matches the input bandwidth. Its 61.6 dB SNR is well-suited for waveform display vertical resolution and for general-purpose signal analysis where 8-9 effective bits suffice. The integrated reference eliminates the cost and layout effort of an external reference IC, while the parallel CMOS output feeds directly into an FPGA capture buffer at full sample rate. Designers building modular DAQ platforms can also take advantage of the pin-compatible CDK1307 (40 MSPS) family to offer multiple bandwidth SKUs from the same PCB layout, streamlining the bill of materials across product variants.
Recomendado
Industrial Line-Scan and Machine Vision Cameras
The CDK1308DILP40 supports line-scan camera front-ends used in factory-automation quality inspection, web/print inspection systems, and conveyor sorting equipment where high line rates (matched to encoder feedback) drive sampling throughput requirements. Its 80 MSPS sample rate lets designers capture high-speed moving webs and rotating shafts with sub-pixel accuracy, while the 46 mW power dissipation keeps thermal loading low on compact line-scan PCBs mounted close to the optical path. The industrial -40C to +85C operating range covers factory-floor temperature extremes without derating, and the 40-pin QFN (6x6 mm) provides adequate thermal mass for continuous industrial operation. Coupled with the internal voltage reference, the CDK1308DILP40 enables compact IP67-rated inspection heads with minimal external BOM.
Recomendado
Communications Baseband Digitisation
The CDK1308DILP40 fits low-cost baseband I/Q digitisation in narrowband radio receivers, software-defined radio (SDR) front-ends at IF frequencies up to ~30 MHz, and telemetry receivers where 80 MSPS 10-bit sampling provides 4x Nyquist margin for typical 5-10 MHz IF signals. The 61.6 dB SNR at 8 MHz input translates into effective noise figure of around 30 dB when paired with a typical front-end LNA, adequate for amateur-radio, telemetry, and ISM-band receivers where dynamic range is secondary to cost and power. The wide digital I/O supply range lets the ADC interface directly to inexpensive 1.8 V or 3.3 V microcontrollers or DSPs used in entry-level SDR platforms, avoiding extra level-shift complexity on the parallel output bus.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para CDK1308DILP40 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | CDK1308CILP40 | CDK1307CILP40 | ADS901E/1KG4 | ADS8342IBPFBR |
|---|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | MaxLinear | Texas Instruments | Texas Instruments |
| Package | 40-pin QFN (6x6 mm) | 40-pin QFN (6x6 mm) - same | 40-pin QFN (6x6 mm) - same | 28-pin SOIC - different | 48-pin TQFP - different |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 16 bit |
| Max Sampling Rate | 80 MSPS | 80 MSPS | 40 MSPS | 20 MSPS | 200 kSPS |
| Architecture | Pipeline | Pipeline | Pipeline | Pipeline | SAR |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 5 V | 2.7 V to 5.5 V |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Serial / Parallel |
Diferenciadores clave
- Pin-compatible with the slower CDK1307 family (same 40-QFN footprint, same die family) (frente a ADS901E)
- Internal voltage reference - no external reference IC needed (frente a ADS8508IBDWRG4)
- Ultra-low 46 mW power dissipation at 80 MSPS (frente a CDK1308CILP40)
Notas de diseño
The CDK1308DILP40 has separate analog (AVDD) and digital (DVDD/DRVDD) supply pins. Estimate: a 1.8 V LDO with at least 100 mA headroom is recommended; place a 10 uF bulk capacitor plus 0.1 uF and 1 nF ceramic decoupling caps within 2-3 mm of each supply pin. The internal bias generator requires the BIAS pin to be decoupled with a 10 uF X7R capacitor to REFGND for stable operation across the full 80 MSPS range. Without proper decoupling the 61.6 dB SNR figure may degrade by several dB.
The 40-pin QFN package has an exposed thermal pad that must be soldered to a continuous ground pour for thermal dissipation and electrical grounding. Route all analog and digital grounds on separate inner layers using a star-ground topology that meets at the exposed pad. Place the analog input trace in a 50 ohm controlled-impedance microstrip on the top layer and keep it at least 3 line-widths away from any digital output trace or clock line to avoid coupling. Estimated: for 80 MSPS operation the output bus must be length-matched within 1 mm to preserve data-edge timing across D0-D9.
Estimated: a common pitfall is feeding the CDK1308DILP40 from a noisy switching regulator on the same board. With 46 mW analog dissipation the ADC rejects high-frequency noise well, but at low input frequencies (audio / baseband) downstream coupling can dominate - place a ferrite bead plus 100 ohm resistor between the upstream DC-DC and the ADC's AVDD pin. Designers also frequently forget to connect the exposed pad (pin 40 / EP) on the QFN package; an unconnected EP creates both a thermal and a ground-return discontinuity that can shave 2-3 dB off the SNR figure.
Información de cumplimiento
RoHS-compliant per MaxLinear product page; AEC-Q100 qualification not indicated for the CDK1308D family - choose an AEC-Q100 part if automotive.
