DSPIC33CK128MC106-I/PT - 16-bit DSC 128KB Flash 64-TQFP | Microchip
N.º de pieza: DSPIC33CK128MC106-I/PT ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $2.86 | $2,86 |
| 10 | $2.61 | $26,10 |
| 100 | $2.34 | $234,00 |
| 500 | $2.2 | $1.100,00 |
| 1.000 | $2.05 | $2.050,00 |
DSPIC33CK128MC106-I/PT Descripción general
A digital signal controller combines the compute architecture of a microcontroller with the mathematical throughput of a digital signal processor. In the power-management hierarchy, a DSC sits above general-purpose MCUs for control-loop-intensive tasks: it executes a complete current-loop compensation cycle in a single PWM period, which is the defining requirement of modern digital power conversion and motor control. The dsPIC33CK family is Microchip's single-core, 16-bit DSC generation built for exactly these closed-loop workloads.
Key differentiating features include the 100 MIPS single-core CPU with DSP engine (single-cycle MAC, 40-bit accumulator, barrel shifter), 128KB of Flash with live self-programming, a 12-bit 3.5 Msps ADC supporting multiple simultaneous sampling channels, on-chip op amps that eliminate external signal-conditioning stages, and high-resolution PWM peripherals with dedicated time base for phase-shifted and complementary converter topologies. On-chip CAN FD enables in-vehicle and industrial bus connectivity at data rates beyond classic CAN.
Architecturally, the dsPIC33CK core uses a modified Harvard pipeline with zero-overhead loops and hardware division support, letting control firmware sustain FOC (field-oriented control) or average-current-mode loops at tens of kHz without CPU starvation. The peripheral Trigger and Interrupt routing system ties ADC sampling directly to PWM event timing, producing deterministic, low-jitter control loops.
Typical applications include brushless DC and PMSM motor drives for industrial automation, digitally controlled AC-DC and DC-DC power supplies, automotive and industrial CAN FD nodes, and power-factor-correction stages. The combination of fast ADC, flexible PWM, and on-chip amplification makes a single DSPIC33CK128MC106-I/PT sufficient for an entire digital power control stage.
A key design consideration is temperature grade selection: the -I suffix specifies -40C to +125C operation; use the -E or automotive-grade -H variants for harsher environments. Decouple VDD/VDDCORE rails per the manufacturer datasheet and route PWM traces away from analog ADC inputs.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, with prices as of 2026-09-22.
Alternativas directas para DSPIC33CK128MC106-I/PT — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con DSPIC33CK128MC106-I/PT (mismo factor de forma y huella) — difiere en PWM, Package, ADC Resolution, Operating Temperature, Core.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
DSPIC33CK128MC106-E/PT
✅ Sustitución directa✓ En stock
$4.2 / unidad
Ver hoja de datos →DSPIC33CK256MC106-I/PT
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
DSPIC33CK64MC106-I/PT
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
DSPIC33CK128MC105-I/PT
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$3.48 / unidad
Ver hoja de datos →DSPIC33CK128MC106-H/PT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DSPIC33CK128MC106-I/PT Valores máximos y características eléctricas
| Core Architecture | 16-bit dsPIC DSC, single core |
| Core Speed | 100 MIPS |
| Flash Program Memory | 128KB (128K x 8) |
| Data Memory (RAM) | 16KB |
| ADC Resolution | 12-bit |
| ADC Sample Rate | 3.5 Msps |
| PWM | High-speed PWM |
| Communication Interfaces | CAN FD, UART, SPI, I2C |
| On-chip Op Amps | Yes |
| Temperatura de funcionamiento | -40C to +125C (industrial, -I grade) |
| Encapsulado | 64-TQFP (10x10 mm) |
| Tipo de montaje | Surface Mount |
| Programmability | ICSP via PGECx/PGEDx pairs |
| DSP Engine | Single-cycle MAC, 40-bit accumulator |
| Estado RoHS | Compliant |
| Estado del ciclo de vida | Active |
Guía de configuración de pines de DSPIC33CK128MC106-I/PT 64-tqfp (10x10 mm)
Configuración de pines para DSPIC33CK128MC106-I/PT (encapsulado 64-tqfp (10x10 mm)). Este CI digital incluye GPIO, interfaces de comunicación (UART, SPI, I2C) y pines de alimentación. Consulte la hoja de datos del fabricante para conocer las funciones alternativas de los pines y las opciones de configuración. Esencial para el diseño de sistemas embebidos y el diseño de PCB.
No hay datos detallados de patillaje disponibles para DSPIC33CK128MC106-I/PT.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
DSPIC33CK128MC106-I/PT es adecuado para 6 aplicacións: BLDC / PMSM Motor Control, Digital Power Conversion (AC-DC / DC-DC), Automotive CAN FD Nodes, Power Factor Correction (PFC) Stages, Industrial Sensing and Edge Control, Robotics and Servo Drives.
BLDC / PMSM Motor Control
The DSPIC33CK128MC106-I/PT fits brushless DC and PMSM drives because its 100 MIPS core executes field-oriented control inner loops at 20-50 kHz while the high-speed PWM generates complementary gate signals with hardware dead-time insertion. The 12-bit ADC samples phase currents synchronized to PWM events, minimizing ripple-induced measurement error, and on-chip op amps amplify low-side shunt signals without external amplifiers. Placed as the single digital controller between gate drivers and the CAN FD or UART supervisory bus, it delivers deterministic control latency; the trade-off versus dual-core dsPIC33CH parts is that communication and control share one core.
Recomendado
Digital Power Conversion (AC-DC / DC-DC)
In digitally controlled power supplies, the DSPIC33CK128MC106-I/PT implements average-current-mode or voltage-mode loops using its dedicated high-speed PWM with phase-shifted outputs for full-bridge and LLC topologies. The 3.5 Msps 12-bit ADC samples output voltage and inductor current once per switching cycle, and the 100 MIPS DSP engine with single-cycle MAC sustains compensation math without cycle stealing. On-chip op amps condition current-shunt signals internally, reducing component count. The CAN FD or UART interface enables PMBus-style telemetry to a system host, and programmable fault protection trips PWM outputs within one clock cycle on overcurrent events.
Recomendado
Automotive CAN FD Nodes
The integrated CAN Flexible Data-Rate module makes the DSPIC33CK128MC106-I/PT well suited to automotive and industrial bus nodes that also perform local control, such as electric power steering assist logic, pump drives, and thermal-management actuators. CAN FD carries 64-byte payloads at faster data phases than classic CAN, and the 100 MIPS core handles both the protocol stack and a control loop concurrently. For harsh under-hood environments, select the AEC-Q100 qualified DSPIC33CK128MC106-H/PT variant rated to +150C. An external CAN transceiver with proper bus termination completes the physical layer.
Recomendado
Power Factor Correction (PFC) Stages
The DSPIC33CK128MC106-I/PT suits boost-PFC and bridgeless-totem-pole-PFC controllers because high-resolution PWM phase control and fast ADC sampling align the inductor-current waveform to line voltage with low THD. The 100 MIPS core runs notch filtering and feedforward compensation in real time, while on-chip op amps buffer current-shunt and AC-line sensing signals. Hardware comparators provide cycle-by-cycle overcurrent limiting independent of software. Running the PFC loop on the same controller as a downstream DC-DC converter stage permits coordinated soft-start and fault propagation through internal signals rather than external wiring.
Recomendado
Industrial Sensing and Edge Control
With a 12-bit ADC, on-chip op amps, SPI and I2C peripherals, the DSPIC33CK128MC106-I/PT serves as a smart sensor front end and local actuator controller in factory automation. The op amps amplify sensor outputs such as pressure bridges or thermocouple-conditioned signals before ADC conversion, and the DSP engine applies digital filtering in real time. The 64-TQFP (10x10 mm) package provides enough GPIO for multiplexed sensor channels, while the UART links to a gateway PLC node. Its -40C to +125C industrial temperature rating supports sealed enclosures and panel-mounted electronics without derating.
Recomendado
Robotics and Servo Drives
Robot joint servo drives benefit from the DSPIC33CK128MC106-I/PT combination of fast current-loop sampling, encoder interface capability via its capture/QEI peripherals, and CAN FD connectivity to the robot controller. The 100 MIPS core cascades position, velocity, and current control loops at kHz rates with deterministic timing, and the high-speed PWM drives H-bridges or three-phase inverters with precise dead-time. On-chip op amps condition dual-shunt current sensing, and the -40C to +125C industrial grade tolerates enclosed actuator thermal rise. The 128KB Flash stores trajectory interpolation tables and drive firmware with headroom for field updates.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para DSPIC33CK128MC106-I/PT — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | DSPIC33CK128MC106-E/PT | DSPIC33CK256MC106-I/PT | DSPIC33CK64MC106-I/PT | DSPIC33CK128MC106-H/PT |
|---|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Program Memory | 128KB | 128KB | 256KB | 64KB | 128KB |
| RAM | 16KB | 16KB | 16KB | 16KB | 16KB |
| Core Speed | 100 MIPS | 100 MIPS | 100 MIPS | 100 MIPS | 100 MIPS |
| Operating Temperature | -40C to +125C | -40C to +150C (extended) | -40C to +125C | -40C to +125C | -40C to +150C (automotive, AEC-Q100) |
| CAN FD | Yes | Yes | Yes | Yes | Yes |
| AEC-Q100 Qualification | No (industrial grade) | No (extended temp) | No | No | Yes |
Diferenciadores clave
- High-temperature industrial standard grade (frente a DSPIC33CK128MC106-E/PT)
- CAN FD connectivity as standard (frente a DSPIC33EP128MC206-I/PT)
- Cost-optimized Flash sizing (frente a DSPIC33CK256MC106-I/PT)
- Automotive qualification path on the same footprint (frente a DSPIC33CK128MC106-H/PT)
Notas de diseño
Provide a solid ground plane under the 64-TQFP and decouple all VDD pins with 100 nF ceramics placed within 2 mm of each pin, plus bulk 10 uF per supply domain. Keep the ADC reference (VREF+/AVSS) traces short, star-routed to a quiet analog ground region. The dsPIC33CK configuration bits allow peripheral pin remapping - define PPS assignments early so PWM outputs, ADC inputs, and PGECx/PGEDx ICSP pairs (must be used as matched pairs, e.g., PGEC2/PGED2) land on pads with correct routing.
Estimated: the 64-TQFP (10x10 mm) junction-to-ambient thermal resistance for a standard 4-layer JEDEC board is typically on the order of 40-50 C/W; verify the exact value in the manufacturer datasheet package thermal appendix for your stackup. At 100 MHz core operation with heavy peripheral loading, power consumption remains well within passive-cooling limits, but in sealed enclosures above 85C ambient, consider the -E extended-temperature variant and validate junction temperature against the +125C rating.
Route high-speed PWM outputs away from analog ADC input traces to prevent gate-driver switching noise from corrupting current-sense samples. Use the ADC trigger sourced from the PWM module to sample phase currents at the center of the PWM off-time, where ripple is minimized - this is a documented best practice in Microchip's dsPIC33CK motor control reference designs. Twisted-pair or guarded routing for shunt signals further reduces common-mode noise at 3.5 Msps sampling rates.
Do not mix PGECx/PGEDx pairs during ICSP: per northernsoftware.com, the DSPIC33CK128MC106 has multiple programming pairs, but ICSPCLK and ICSPDAT must come from the same pair. Also, flash programming, configuration words, and code protection must be set intentionally - incorrect configuration bits can disable debugging access. Finally, migration between dsPIC33EP and dsPIC33CK generations is NOT pin-compatible despite both offering 64-TQFP packages; validate the pinout table before reusing an existing PCB.
Información de cumplimiento
RoHS compliance and lead-free assembly per standard Microchip product offerings for the -I/PT industrial grade. AEC-Q100 qualification applies only to the -H/PT automotive variant. REACH and conflict-minerals status not stated in the provided data.
