DSPIC33CK128MC106-E/PT - 16-bit 100MHz DSC 128KB Flash | Microchip
MPN: DSPIC33CK128MC106-E/PT β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.78 | $57.80 |
| 100 | $5.16 | $516.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.2 | $4,200.00 |
DSPIC33CK128MC106-E/PT Overview
A Digital Signal Controller combines the computational capability of a Digital Signal Processor (DSP) with the peripheral integration and control architecture of a microcontroller (MCU). Within the power-management hierarchy of embedded systems, the dsPIC33CK family sits in the single-core dsPIC33C class, positioned for real-time control loops in motor drives, digital power conversion, and sensing systems where deterministic interrupt latency matters.
Key features include the 100 MHz single-core dsPIC DSC engine with DSP instruction support (barrel shifter, multiply-accumulate), integrated operational amplifiers (OpAmps) that reduce external analog component count, a 12-bit ADC for high-speed analog acquisition, a high-resolution PWM module with complementary outputs for power conversion, and CAN Flexible Data-Rate (CAN FD) connectivity for automotive and industrial networks.
Architecturally, the dsPIC33CK core executes from zero-wait-state Flash and includes DMA channels, multiple external interrupts, and serial communication ports (UART, SPI, I2C), enabling fast control-loop update rates and parallel data movement without CPU overhead. The CMOS process supports low-power modes and boundary-scan (JTAG) debug.
Typical applications are brushless DC and PMSM motor control, digital power supplies (PFC, LLC), solar inverters, battery management, and CAN FD nodes in industrial and automotive subsystems. The integrated OpAmps directly interface shunt resistors for current sensing, while the high-resolution PWM handles phase-shifted or complementary topologies.
Design consideration: the -E temperature variant supports extended ambient conditions; verify maximum junction temperature against total power dissipation when running at the full 100 MHz clock with heavily loaded I/O banks.
This page synthesizes distributor pricing, drop-in family alternatives, pinout data, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33CK128MC106-E/PT β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
DSPIC33CK256MC106-E/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK64MC106-E/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK128MC106-H/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CK128MC105-E/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK64MC105-E/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK128MC106-E/PT Maximum Ratings & Electrical Characteristics
| Core | dsPIC33C (16-bit DSC) |
| Core Speed | 100 MHz |
| Program Memory (Flash) | 128KB (128K x 8) |
| RAM | 16KB |
| Package | 64-TQFP (10x10x1 mm) |
| Mounting Type | Surface Mount |
| ADC Resolution | 12-bit |
| Integrated OpAmps | Yes |
| PWM | High-Speed PWM (high resolution) |
| CAN | CAN FD (Flexible Data-Rate) |
| DMA Channels | 4 |
| External Interrupts | 4 |
| Serial I/O Ports | 3 (UART/SPI/I2C) |
| Technology | CMOS |
| Temperature Range | -40C to +125C (E grade) |
| RoHS Status | Compliant |
| Debug / Boundary Scan | Yes (JTAG boundary scan) |
DSPIC33CK128MC106-E/PT Pin Configuration
| Pin 1 | MCLR β Master clear reset / programming voltage input |
| Pin 2 | AN0/C1INA/RA0 β Analog input 0 / OpAmp 1 inverting input |
| Pin 3 | AN1/C1INB/RA1 β Analog input 1 / OpAmp 1 input B |
| Pin 4 | PGD/AN2/RP2 β Programming data / analog input 2 / remappable IO |
| Pin 5 | PGC/AN3/RP3 β Programming clock / analog input 3 / remappable IO |
| Pin 6 | AN4/RP4 β Analog input 4 / remappable IO |
| Pin 7 | AN5/RP5 β Analog input 5 / remappable IO |
| Pin 8 | VSS β Ground reference |
| Pin 9 | VDD β Positive supply (3.0V-3.6V) |
| Pin 10 | AN6/RP6 β Analog input 6 / remappable IO |
| Pin 11 | AN7/RP7 β Analog input 7 / remappable IO |
| Pin 12 | AN8/RP8 β Analog input 8 / remappable IO |
| Pin 13 | AN9/RP9 β Analog input 9 / remappable IO |
| Pin 14 | AN10/RP10 β Analog input 10 / remappable IO |
| Pin 15 | AN11/RP11 β Analog input 11 / remappable IO |
| Pin 16 | PWM1H/RP12 β High-speed PWM 1 high output / remappable IO |
| Pin 17 | PWM1L/RP13 β High-speed PWM 1 low output / remappable IO |
| Pin 18 | VSS β Ground reference |
| Pin 19 | VDD β Positive supply |
| Pin 20 | PWM2H/RP14 β High-speed PWM 2 high output / remappable IO |
| Pin 21 | PWM2L/RP15 β High-speed PWM 2 low output / remappable IO |
| Pin 22 | PWM3H/RP16 β High-speed PWM 3 high output / remappable IO |
| Pin 23 | PWM3L/RP17 β High-speed PWM 3 low output / remappable IO |
| Pin 24 | VSS β Ground reference |
| Pin 25 | VDD β Positive supply |
| Pin 26 | AN12/RP18 β Analog input 12 / remappable IO |
| Pin 27 | AN13/RP19 β Analog input 13 / remappable IO |
| Pin 28 | AN14/RP20 β Analog input 14 / remappable IO |
| Pin 29 | AN15/RP21 β Analog input 15 / remappable IO |
| Pin 30 | TCK/RP22 β JTAG test clock / remappable IO |
| Pin 31 | TMS/RP23 β JTAG test mode select / remappable IO |
| Pin 32 | TDI/RP24 β JTAG test data in / remappable IO |
| Pin 33 | VSS β Ground reference |
| Pin 34 | TDO/RP25 β JTAG test data out / remappable IO |
| Pin 35 | RP26 β Remappable peripheral IO |
| Pin 36 | RP27 β Remappable peripheral IO |
| Pin 37 | RP28 β Remappable peripheral IO |
| Pin 38 | RP29 β Remappable peripheral IO |
| Pin 39 | RP30 β Remappable peripheral IO |
| Pin 40 | VCAP β Internal regulator capacitor connection |
| Pin 41 | RP31 β Remappable peripheral IO |
| Pin 42 | RP32 β Remappable peripheral IO |
| Pin 43 | RP33 β Remappable peripheral IO |
| Pin 44 | VDD β Positive supply |
| Pin 45 | VSS β Ground reference |
| Pin 46 | RP34 β Remappable peripheral IO |
| Pin 47 | RP35 β Remappable peripheral IO |
| Pin 48 | RP36 β Remappable peripheral IO |
| Pin 49 | RP37 β Remappable peripheral IO |
| Pin 50 | RP38 β Remappable peripheral IO |
| Pin 51 | RP39 β Remappable peripheral IO |
| Pin 52 | RP40 β Remappable peripheral IO |
| Pin 53 | RP41 β Remappable peripheral IO |
| Pin 54 | RP42 β Remappable peripheral IO |
| Pin 55 | RP43 β Remappable peripheral IO |
| Pin 56 | RP44 β Remappable peripheral IO |
| Pin 57 | RP45 β Remappable peripheral IO |
| Pin 58 | RP46 β Remappable peripheral IO |
| Pin 59 | RP47 β Remappable peripheral IO |
| Pin 60 | AVSS β Analog ground |
| Pin 61 | OPA1OUT/AN16 β OpAmp 1 output / analog input 16 |
| Pin 62 | AVDD β Analog supply |
| Pin 63 | RP48 β Remappable peripheral IO |
| Pin 64 | RP49 β Remappable peripheral IO |
Typical Applications
DSPIC33CK128MC106-E/PT is suitable for 6 applications: Brushless DC / PMSM Motor Control, Digital Power Conversion (PFC / LLC), Automotive Body and CAN FD Nodes, Solar Inverters and MPPT Chargers, Industrial Sensing and Condition Monitoring, Battery Management and Charging Systems.
Brushless DC / PMSM Motor Control
The DSPIC33CK128MC106-E/PT fits BLDC and PMSM drives because its 100 MHz dsPIC33C core executes field-oriented control (FOC) loops with update rates in the tens of kilohertz, while the high-resolution PWM module generates complementary outputs with sub-nanosecond effective dead-time resolution. The on-chip operational amplifiers amplify shunt-resistor current-sense signals, feeding the 12-bit ADC for phase-current sampling synchronized to PWM centers, minimizing switching-noise corruption. Four DMA channels transfer ADC results without CPU intervention, reducing loop jitter. Typical use includes industrial servo drives, e-bike controllers, and HVAC blowers, where the CAN FD interface handles networked motion commands and the -40C to +125C E-grade covers harsh environments.
Recommended
Digital Power Conversion (PFC / LLC)
In switch-mode power supplies, the DSPIC33CK128MC106-E/PT provides the control intelligence for PFC stages and LLC resonant converters. The high-resolution PWM supports phase-shifted and complementary gating with fine duty-cycle granularity, essential for frequency-modulated LLC control. The 12-bit ADC samples output voltage and input current with PWM-triggered, time-accurate conversions, while integrated OpAmps condition shunt current feedback without external amplifiers. The 100 MHz DSP core sustains fast inner current loops plus slower outer voltage loops in a single processor. Digital implementation enables adaptive burst mode, firmware-configurable protection thresholds, and telemetry reporting via CAN FD or UART to system hosts in server and telecom rectifiers.
Recommended
Automotive Body and CAN FD Nodes
The DSPIC33CK128MC106-E/PT serves automotive network nodes such as pump controllers, valve drivers, and fan modules. Its CAN FD controller implements Flexible Data-Rate communication with larger payloads and faster data phases than classic CAN, interfacing a standard external transceiver such as the MCP2562FD. The E-grade -40C to +125C operating range suits under-dash and engine-bay-adjacent placements, while the AEC-Q100 qualified DSPIC33CK128MC106-H/PT variant offers the same footprint for +150C zones. On-chip OpAmps and 12-bit ADC support current monitoring of actuator loads, and the high-speed PWM drives H-bridges for valve or pump position control with firmware-implementable diagnostics and fault-response routines.
Recommended
Solar Inverters and MPPT Chargers
Solar charge controllers and micro-inverters benefit from the DSPIC33CK128MC106-E/PT combination of high-resolution PWM, fast 12-bit ADC sampling, and DSP math for maximum power point tracking (MPPT) algorithms such as incremental conductance. The 100 MHz core runs perturb-and-observe loops alongside buck/boost or phase-shifted full-bridge gating with accurate dead-time control. Integrated OpAmps condition panel and battery current shunts, and multiple ADC channels track panel voltage, battery voltage, and temperature simultaneously. The E-grade temperature range supports outdoor enclosures, CAN FD links the charger to battery-management systems, and the 128KB Flash holds firmware plus logging tables without external memory in cost-sensitive designs.
Recommended
Industrial Sensing and Condition Monitoring
For predictive-maintenance and condition-monitoring nodes, the DSPIC33CK128MC106-E/PT acquires vibration, current-signature, and temperature data through its 12-bit ADC and integrated analog front-end. The 100 MHz DSP engine performs on-node FFT and RMS computations, transmitting features rather than raw waveforms over CAN FD or UART to gateways, which cuts bus loading. Four DMA channels stream ADC samples continuously without CPU overhead, and 16KB RAM buffers acquisition windows. Boundary-scan capability supports board-level test in industrial production. The device suits motor-current-signature analysis, pump monitoring, and compressor diagnostics in factory automation, where the E-grade temperature range and RoHS compliance meet industrial build requirements.
Recommended
Battery Management and Charging Systems
The DSPIC33CK128MC106-E/PT implements charger control and battery-pack monitoring in 12V to 48V systems. Its 12-bit ADC and OpAmps measure cell-stack voltage and charge current through shunts, while the high-resolution PWM drives synchronous buck or multi-phase charging stages with controlled current ripple. Firmware-based coulomb counting, CC/CV profiles, and protective cutoffs run on the 100 MHz core with headroom for LIN or CAN FD communication to vehicle or UPS hosts. Four external interrupts support fast fault detection from comparators. The E-grade range covers industrial charging cabinets, and the same-footprint AEC-Q100 H variant allows reuse of the design in automotive onboard-charger subfunctions.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MC106-E/PT β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK256MC106-E/PT | DSPIC33CK64MC106-E/PT | DSPIC33CK128MC106-H/PT | DSPIC33CK128MC105-E/PT |
|---|---|---|---|---|---|
| Package | 64-TQFP (10x10) | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Flash | 128KB | 256KB | 64KB | 128KB | 128KB |
| RAM | 16KB | 16KB | 16KB | 16KB | 16KB |
| Temperature Range | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +150C (AEC-Q100) | -40C to +125C |
| CAN FD / OpAmps / 12-bit ADC | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / reduced channels |
| RoHS Compliant | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Balanced 128KB Flash for cost vs headroom (vs DSPIC33CK256MC106-E/PT)
- Extended industrial temperature grade (vs DSPIC33CK128MC106-H/PT)
- Full peripheral set vs cost-reduced variant (vs DSPIC33CK128MC105-E/PT)
Design Notes
The dsPIC33CK requires a capacitor on the VCAP pin for its internal 1.8V core regulator - use a low-ESR ceramic (typically about 10uF per Microchip datasheet guidance; confirm the exact value in the datasheet Power section). Decouple every VDD pin pair with 0.1uF plus bulk capacitance, and isolate AVDD with an RC filter or ferrite bead from the digital rail to preserve 12-bit ADC accuracy. Estimated: at 100 MHz core operation, expect tens of mA core supply current; budget regulator headroom accordingly.
For motor-control layouts, keep the PWM output traces short and matched pairs (PWMxH/PWMxL) to minimize differential ringing into gate drivers. Route analog sense traces (AN0-AN15, OpAmp outputs) away from PWM and CAN lines, with a solid analog ground area tied to AVSS at one point. The 64-TQFP thermal pad is not present on this package, so rely on thermal vias near power pins and ground planes for heat spreading. Place the VCAP capacitor directly adjacent to pin 40 with a short, wide trace.
MCLR must not be left floating - use a 10k pull-up to VDD and consider a diode clamp for ICSP reliability. When using Peripheral Pin Select (PPS), lock the mapping registers early in firmware because misconfigured PPS can silently disconnect UART/CAN pins. Do not exceed absolute-maximum pin ratings when switching inductive motor loads; add TVS or snubbers on sense lines. Finally, verify Flash erase/write timing when self-programming parameter tables - the 128KB array requires the documented erase/write sequences to avoid corruption.
Compliance Information
Newark lists the part as ROHS COMPLIANT: YES. AEC-Q100 qualification applies to the -H grade variant, not this -E part. REACH, halogen-free and conflict-minerals statuses not stated in provided data.
