EP2AGX95EF35C4G - Arria II GX FPGA 95K LE FCBGA-1152 | Intel
N.º de pieza: EP2AGX95EF35C4G ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $1850 | $1.850,00 |
| 10 | $1780 | $17.800,00 |
| 100 | $1690 | $169.000,00 |
| 250 | $1620 | $405.000,00 |
| 500 | $1555 | $777.500,00 |
EP2AGX95EF35C4G Descripción general
What is an FPGA? An FPGA (Field-Programmable Gate Array) is a semiconductor IC whose logic fabric, interconnect, and I/O behavior are defined by user-supplied configuration data rather than fixed at the fab. FPGAs sit within the broader taxonomy of programmable logic devices -> programmable logic -> digital semiconductors -> integrated circuits. The Arria II GX family targets mid-range applications requiring a balance of high-speed transceivers, on-chip memory, DSP blocks, and cost-effective logic density for protocol bridging, video processing, and wireless baseband.
Key features of the EP2AGX95EF35C4G include up to 4 integrated 3.75 Gbps transceivers (8 total channels when configured in bonded mode) with hard PCIe Gen1/Gen2 and multiple protocol support; 616 embedded 18x18 multipliers for DSP; 4 PLLs; configurable LVDS, LVTTL, LVCMOS, and SSTL I/O standards; and hard memory controllers. The device supports partial and remote configuration via passive serial, fast passive parallel, and JTAG modes, and is supported by Quartus II design software (legacy compatibility per Arria II family).
Typical applications include high-speed serial protocol bridging (PCIe Gen2, Serial RapidIO, Gbps Ethernet, CPRI/OBSAI), video broadcast infrastructure, wireless baseband processing, military secure communications, and ASIC prototyping. The 452 user I/O count and 6.5 Mbit embedded RAM also suit high-throughput data-acquisition front ends.
When designing with this device, allocate the largest possible BGA break-out escape region in your PCB stackup and follow Intel's recommended 1.0 mm pitch land-pattern rules. Use multiple 0.1 uF + 10 uF decoupling groups per power pin and tie all unused transceiver inputs to ground through 1 kohm to prevent spurious emissions.
This page synthesizes distributor pricing, drop-in same-package alternatives from the Arria II family, and practical design notes not aggregated on any single manufacturer or distributor page.
Alternativas directas para EP2AGX95EF35C4G — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con EP2AGX95EF35C4G (mismo factor de forma y huella) — difiere en Package, Logic Elements, Embedded Memory Bits, Process Technology, Speed Grade.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
EP2AGX125EF35C4G
✅ Sustitución directa✓ En stock
$1290 / unidad
Ver hoja de datos →EP2AGX190FF35C4G
✅ Sustitución directa✓ En stock
$2350 / unidad
Ver hoja de datos →EP2AGX260FF35C4G
✅ Sustitución directa✓ En stock
$1420 / unidad
Ver hoja de datos →EP2AGX95EF29I5N
✅ Sustitución directa✓ En stock
$1320 / unidad
Ver hoja de datos →EP2AGX95DF25C4G
✅ Sustitución directa✓ En stock
$360 / unidad
Ver hoja de datos →EP2AGX95EF35C4G Valores máximos y características eléctricas
| Family | Arria II GX |
| Logic Elements (LE) | 89,178 |
| Embedded Memory Bits | 6,839,296 bits (~6.5 Mbit) |
| Embedded 18x18 Multipliers | 616 |
| User I/Os | 452 |
| Transceiver Blocks | 4 (up to 3.75 Gbps) |
| PCIe Hard IP | Gen1/Gen2 (x1/x2/x4) |
| PLLs | 4 |
| Process Technology | 40 nm TSMC low-power |
| Speed Grade | -4 (mid-speed) |
| Temperatura de funcionamiento | 0C to +85C (commercial) |
| Encapsulado | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Configuration Mode | Passive Serial, Fast Passive Parallel, JTAG |
| Core Voltage | 0.9 V nominal |
| Estado RoHS | Compliant |
Guía de configuración de pines de EP2AGX95EF35C4G 1152-ball fcbga, 35 mm x 35 mm, 1.0 mm pitch
Configuración de pines para EP2AGX95EF35C4G (encapsulado 1152-ball fcbga, 35 mm x 35 mm, 1.0 mm pitch). Este CI digital incluye GPIO, interfaces de comunicación (UART, SPI, I2C) y pines de alimentación. Consulte la hoja de datos del fabricante para conocer las funciones alternativas de los pines y las opciones de configuración. Esencial para el diseño de sistemas embebidos y el diseño de PCB.
No hay datos detallados de patillaje disponibles para EP2AGX95EF35C4G.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
EP2AGX95EF35C4G es adecuado para 7 aplicacións: High-Speed Serial Protocol Bridging, Wireless Baseband Processing, Video Broadcast and Studio Infrastructure, ASIC Prototyping and Emulation, Military and Secure Communications, Industrial Test and Measurement, Medical Imaging Front Ends.
High-Speed Serial Protocol Bridging
The EP2AGX95EF35C4G integrates 4 hardened 3.75 Gbps transceiver channels with built-in PCIe Gen1/Gen2, Serial RapidIO, Gbps Ethernet, and CPRI/OBSAI physical coding sublayers, eliminating the need for external PHY ICs in protocol-bridging applications. With 89K LE and 616 18x18 multipliers, the FPGA can simultaneously run a CPRI framer, a custom MAC, and packet classification logic. Designers place the EP2AGX95EF35C4G between a baseband ASIC and a backhaul framer; its 452 user I/Os expose parallel LVDS lanes for chip-to-chip interconnect. Compared with a discrete PHY plus CPLD approach, the integrated transceiver reduces board area by roughly 40% and BOM cost by 25-35%.
Recomendado
Wireless Baseband Processing
The 616 embedded 18x18 multipliers and 6.5 Mbit of block RAM make the EP2AGX95EF35C4G well-suited for small-cell and picocell baseband signal processing at LTE and 3G rates. The 4 transceiver blocks handle CPRI up to 3.072 Gbps to connect the baseband card with the radio unit, while the LE fabric runs channel estimation, FFT/iFFT, and turbo decoder cores. The commercial 0C to +85C temperature range covers indoor small-cell enclosures and outdoor cabinets with modest thermal management. Designers typically allocate 60-70% of logic for PHY-layer DSP and reserve 20% for MAC scheduling and backhaul interfacing.
Recomendado
Video Broadcast and Studio Infrastructure
Studio routers, format converters, and contribution encoders benefit from the EP2AGX95EF35C4G's 452 user I/Os that can be configured as LVDS pairs to ingest SDI signals, and the 89K LE that runs multi-rate SDI processing cores. The device's on-chip memory buffers line-store data without external DDR, simplifying PCB layout for 3G-SDI and 6G-SDI routers. The 4 PLLs generate independent video clocks for SD, HD, 3G, and 4K formats. Compared to ASIC alternatives, the FPGA approach lets broadcast OEMs ship a single hardware platform with feature upgrades via firmware.
Recomendado
ASIC Prototyping and Emulation
The EP2AGX95EF35C4G serves as a cost-effective ASIC prototyping vehicle for mid-complexity SoCs, providing 89K LE of mapped logic plus hardened transceivers for real-world interface validation. Engineers partition the ASIC RTL across multiple FPGAs using Time Division Multiplexing (TDM) when the design exceeds 89K LE. The 6.5 Mbit embedded memory approximates the ASIC's distributed SRAM, allowing software teams to validate drivers and firmware pre-tapeout. Quartus II supports incremental compile flows that preserve timing closure across iterations.
Recomendado
Military and Secure Communications
Defense integrators use the EP2AGX95EF35C4G as the processing core in tactical radios, encrypted data links, and SIGINT receivers where the hardened transceivers provide secure physical-layer interfaces and the FPGA fabric runs custom cryptographic IP. While the -C4 grade is commercial temperature, the same silicon can be supplied as -I4 or -M5 grades for industrial and military temperature ranges through Intel's part-numbering system. The 452 I/Os support multiple parallel ADC/DAC interfaces commonly found in EW systems. Designers should consult Intel's military product roadmap for long-life-cycle commitments.
Recomendado
Industrial Test and Measurement
High-end oscilloscopes, logic analyzers, and protocol analyzers leverage the EP2AGX95EF35C4G's parallel I/O bandwidth and 3.75 Gbps transceivers to aggregate multiple acquisition channels. The FPGA performs real-time triggering, decimation, and protocol decoding before handing data to a host processor. The 6.5 Mbit embedded memory buffers pre-trigger samples at multi-gigasample rates, while the 452 user I/Os connect to high-speed ADC/DAC mezzanines. The commercial temperature range suits benchtop and laboratory instrumentation.
Recomendado
Medical Imaging Front Ends
Ultrasound beamformers, MRI digitizers, and CT data acquisition front ends use the EP2AGX95EF35C4G to aggregate hundreds of channels of LVDS data from high-speed ADCs and perform preliminary digital signal processing. The 452 user I/Os map to multi-channel LVDS ADC buses; the 616 18x18 multipliers compute digital filtering and beamforming weights; and the on-chip memory caches raw RF data before DMA to external DDR. The 3.75 Gbps transceivers carry processed image data to a host GPU or DSP array over a proprietary or 10G Ethernet link. The commercial temperature range suits climate-controlled clinical environments.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para EP2AGX95EF35C4G — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | EP2AGX125EF35C4G | EP2AGX190FF35C4G | EP2AGX260FF35C4G | EP2AGX95EF29I5N | EP2AGX95DF25C4G |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F35, 35 mm) | 1152-ball FCBGA (F35, 35 mm) - same | 1152-ball FCBGA (F35, 35 mm) - same | 1152-ball FCBGA (F35, 35 mm) - same | 780-ball FCBGA (F29, 29 mm) - different | 780-ball FCBGA (F25, 25 mm) - different |
| Logic Elements | 89,178 | 124,100 | 190,000 | 260,600 | 89,178 | 89,178 |
| Embedded Memory | 6.5 Mbit | 8.3 Mbit | 11.6 Mbit | 16.3 Mbit | 6.5 Mbit | 6.5 Mbit |
| 18x18 Multipliers | 616 | 840 | 1248 | 1672 | 616 | 616 |
| Transceiver Blocks | 4 (up to 3.75 Gbps) | 4 (up to 3.75 Gbps) | 8 (up to 3.75 Gbps) | 12 (up to 3.75 Gbps) | 4 (up to 3.75 Gbps) | 4 (up to 3.75 Gbps) |
| Temperature Grade | Commercial 0C to +85C | Commercial 0C to +85C | Commercial 0C to +85C | Commercial 0C to +85C | Industrial -40C to +100C | Commercial 0C to +85C |
| Speed Grade | -4 | -4 | -4 | -4 | -5 | -4 |
| Approx Unit Price (USD, qty 1) | 1,850 | 2,400 | 3,100 | 4,200 | 1,950 | 1,750 |
Diferenciadores clave
- Highest user I/O count in Arria II GX at mid logic density (frente a EP2AGX95DF25C4G)
- Cost-optimized sweet spot in FCBGA-1152 family (frente a EP2AGX125EF35C4G)
- 4 transceiver blocks at 3.75 Gbps with hardened PCIe Gen2 (frente a EP2AGX65CU17C6G (Cyclone IV E, no transceivers))
Notas de diseño
The FCBGA-1152 package with 1.0 mm ball pitch requires at least an 8-layer PCB stackup with stacked microvia (any-layer HDI preferred) to fan out the inner rows of balls. Use 0.5 oz copper on outer layers and 1.0 oz on inner power/ground planes. Maintain 50 ohm single-ended and 100 ohm differential impedance on all transceiver lanes; place AC-coupling capacitors within 200 mils of the FPGA ball. Reference the Altera Arria II GX F35 package pin-out file and the AN 591: PCB Design for Arria II Devices application note for land-pattern and breakout rules.
Estimated: with all 4 transceivers active at 3.75 Gbps and 60% logic utilization, the EP2AGX95EF35C4G core draws roughly 6-9 W and the transceiver blocks draw 1.5-2.5 W. Decoupling must include one 0.1 uF X7R per power pin within 100 mils, plus 4-8 bulk 10-22 uF X5R capacitors distributed across the FPGA footprint. Use the Quartus II PowerPlay Early Power Estimator (EPE) for accurate pre-layout budgeting; for designs exceeding 10 W, attach a 1-piece heatsink or copper heat-spreader to the package top.
Do not reuse configuration mode pins as user I/O without consulting the latest device handbook; the MSEL pins on the EP2AGX95EF35C4G select the configuration scheme (Passive Serial, Fast Passive Parallel, JTAG) and must be tied to the correct logic level at power-up. All unused transceiver RX inputs must be terminated through 1 kohm resistors to ground to prevent spurious emissions that can cause EMI failures. Finally, the POR (power-on-reset) circuit requires VCCPD ramp time between 0.05 ms and 100 ms - verify your regulator sequencing meets this window or the device will not configure.
Información de cumplimiento
RoHS compliant per the verified distributor data. Halogen-free status is not explicitly stated; AEC-Q100 not applicable for FPGA logic devices in non-automotive applications.
