LTC2155IUP-12 - Dual 12-Bit 170Msps ADC, 1.8V, 64-QFN | Analog Devices
N.º de pieza: LTC2155IUP-12 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $62.52 | $62,52 |
| 10 | $59.4 | $594,00 |
| 100 | $56.27 | $5.627,00 |
| 500 | $53.14 | $26.570,00 |
| 1.000 | $50.02 | $50.020,00 |
LTC2155IUP-12 Descripción general
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. Pipelined ADCs use a multi-stage architecture that enables high sampling rates while maintaining moderate resolution and low power. The LTC2155 belongs to the pipelined ADC sub-family of data converters, which sits within the broader category of mixed-signal ICs and signal-chain components.
Key features of the LTC2155-12 family include DDR LVDS outputs for low-noise high-speed data transfer, an optional sample-and-hold front end, a clock duty-cycle stabilizer for jitter-tolerant sampling, and low-power Sleep and Nap modes. The 1.25 GHz full-power input bandwidth allows direct sampling of IF signals. A serial SPI port provides flexible configuration of output modes, gain, and channel selection.
The 1.8V single-supply operation simplifies power-tree design in FPGA or ASIC co-located systems, while DDR LVDS outputs minimize pin count and reduce EMI by carrying data on differential edges. The pipelined core uses calibrated capacitor arrays and shared references between channels to keep channel-to-channel gain and offset matching tight.
Typical applications include communications receivers (LTE/3G/4G base-station digitizers), radar and phased-array antenna IF sampling, broadband test-and-measurement instrumentation, medical imaging front-ends, and high-speed data acquisition systems. The wide input bandwidth also suits digital oscilloscope front-end channels. The pin-compatible 14-bit (LTC2155-14) and lower-speed family members provide upgrade and cost-down paths on the same PCB footprint.
When designing with this device, route the differential analog inputs as length-matched 100-ohm transmission lines, keep the 1.8V analog supply isolated from noisy digital rails, and place the SPI configuration traces away from the LVDS output edges. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and signal-return integrity.
This page synthesizes distributor pricing, family upgrade/downgrade alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternativas directas para LTC2155IUP-12 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con LTC2155IUP-12 (mismo factor de forma y huella) — difiere en Package, Operating Temperature Range, RoHS Status, Number of Channels, Resolution.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
LTC2155CUP-12
✅ Sustitución directa✓ En stock
$44.25 / unidad
Ver hoja de datos →LTC2155IUP-14
✅ Sustitución directa✓ En stock
$107.04 / unidad
Ver hoja de datos →LTC2156IUP-12
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2157IUP-12
✅ Sustitución directa✓ En stock
$64.89 / unidad
Ver hoja de datos →LTC2155IUP-10
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD9268XCPZ-125
✅ Sustitución directa✓ En stock
$30.95 / unidad
Ver hoja de datos →LTC2155IUP-12 Valores máximos y características eléctricas
| Resolución | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 170 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Rango de tensión de entrada | 1.5 Vp-p |
| Full-Power Bandwidth | 1.25 GHz |
| SNR | 68.5 dB |
| SFDR | 90 dB |
| Tensión de alimentación | 1.8 V (single) |
| Total Power Dissipation | 545 mW |
| Output Interface | DDR LVDS |
| Configuration Interface | Serial SPI port |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) |
| Encapsulado | 64-pin QFN (9x9 mm) |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant (#PBF suffix) |
Configuración de pines de LTC2155IUP-12
| Pin 1 | AIN1+ — Channel 1 differential analog input positive |
| Pin 2 | AIN1- — Channel 1 differential analog input negative |
| Pin 3 | SENSE — Reference configuration pin |
| Pin 4 | GND — Ground (must tie to exposed pad) |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | VREF — Reference voltage decoupling |
| Pin 7 | AIN2+ — Channel 2 differential analog input positive |
| Pin 8 | AIN2- — Channel 2 differential analog input negative |
| Pin 9 | GND — Ground |
| Pin 10 | CLK+ — Differential sample clock positive |
| Pin 11 | CLK- — Differential sample clock negative |
| Pin 12 | OGND — Output driver ground |
| Pin 13 | OVDD — Output driver 1.8V supply |
| Pin 14 | OUT1A+ — Channel 1 DDR LVDS output A positive |
| Pin 15 | OUT1A- — Channel 1 DDR LVDS output A negative |
| Pin 16 | OUT1B+ — Channel 1 DDR LVDS output B positive |
| Pin 17 | OUT1B- — Channel 1 DDR LVDS output B negative |
| Pin 18 | OUT2A+ — Channel 2 DDR LVDS output A positive |
| Pin 19 | OUT2A- — Channel 2 DDR LVDS output A negative |
| Pin 20 | OUT2B+ — Channel 2 DDR LVDS output B positive |
| Pin 21 | OUT2B- — Channel 2 DDR LVDS output B negative |
| Pin 22 | OGND — Output driver ground |
| Pin 23 | DCO+ — DDR LVDS data clock output positive |
| Pin 24 | DCO- — DDR LVDS data clock output negative |
| Pin 25 | FCO+ — DDR LVDS frame clock output positive |
| Pin 26 | FCO- — DDR LVDS frame clock output negative |
| Pin 27 | OGND — Output driver ground |
| Pin 28 | OVDD — Output driver 1.8V supply |
| Pin 29 | CS — SPI chip select (active low) |
| Pin 30 | SCK — SPI serial clock |
| Pin 31 | SDI — SPI serial data input |
| Pin 32 | SDO — SPI serial data output |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | MODE — Mode select strap |
| Pin 36 | OGND — Output driver ground |
| Pin 37 | AVDD — Analog 1.8V supply |
| Pin 38 | AVDD — Analog 1.8V supply |
| Pin 39 | GND — Ground |
| Pin 40 | AVDD — Analog 1.8V supply |
| Pin 41 | GND — Ground |
| Pin 42 | AVDD — Analog 1.8V supply |
| Pin 43 | GND — Ground |
| Pin 44 | AVDD — Analog 1.8V supply |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | GND — Ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | GND — Ground |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | GND — Ground |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | GND — Ground |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | GND — Ground |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | GND — Ground |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | GND — Ground |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | AVDD — Analog 1.8V supply |
| Pin 62 | GND — Ground |
| Pin 63 | AVDD — Analog 1.8V supply |
| Pin 64 | GND — Ground |
Aplicaciones típicas
LTC2155IUP-12 es adecuado para 6 aplicacións: Communications Receiver IF Sampling, Radar and Phased-Array Antenna Front-End, Broadband Test and Measurement Instrumentation, Medical Imaging Front-End Digitizer, High-Speed Data Acquisition Systems, Software Defined Radio (SDR) Baseband.
Communications Receiver IF Sampling
The LTC2155IUP-12 suits multi-carrier communications receiver IF-stage digitizers because its dual channels simultaneously sample I/Q or diversity paths at 170 Msps, and the 1.25 GHz full-power bandwidth lets it capture IF frequencies up to ~500 MHz without aliasing. With 90 dB SFDR the converter preserves modulation fidelity for LTE, 4G, and emerging 5G NR signal chains, while DDR LVDS outputs drive directly into FPGAs without level translation.
Recomendado
Radar and Phased-Array Antenna Front-End
In radar and phased-array antenna systems the LTC2155IUP-12's dual simultaneous-sampling channels preserve channel-to-channel phase coherence across antenna elements. Its 1.25 GHz analog input bandwidth supports direct IF sampling at L-band and S-band radar IF frequencies, while 68.5 dB SNR / 90 dB SFDR maintains target detection sensitivity and dynamic range. Pin-compatible 14-bit variants allow upgrade to higher dynamic range without PCB rework.
Recomendado
Broadband Test and Measurement Instrumentation
Test and measurement instruments such as digital oscilloscopes, spectrum analyzers, and signal analyzers use the LTC2155IUP-12 as an input-channel digitizer because its dual channels, 170 Msps real-time sample rate, and 1.25 GHz analog input bandwidth cover bandwidths beyond 100 MHz on each channel. The SPI configuration port allows gain and offset calibration per channel, and DDR LVDS outputs minimize the FPGA pin count required to capture high-speed data streams.
Recomendado
Medical Imaging Front-End Digitizer
Ultrasound and other medical imaging front-ends use the LTC2155IUP-12 because its dual simultaneous sampling captures phased-array transducer channels with precise inter-channel timing. Low power (545 mW total) simplifies thermal management in cart-based portable ultrasound systems, while the 1.8V single supply eases battery-powered operation. The wide input bandwidth supports direct sampling of RF-modulated transducer signals before beamforming.
Recomendado
High-Speed Data Acquisition Systems
Industrial and laboratory data acquisition systems use the LTC2155IUP-12 as a dual-channel simultaneous-sampling digitizer with high dynamic range. The pipelined core delivers low-latency conversions suitable for closed-loop control and event-triggered capture, while the SPI port enables per-channel gain, offset, and channel-selection adjustments. Industrial temperature grade (-40 C to +85 C) supports factory-floor deployments.
Recomendado
Software Defined Radio (SDR) Baseband
Software defined radio platforms use the LTC2155IUP-12 as a baseband or low-IF digitizer because the dual channels directly capture I/Q signal pairs at 170 Msps, supporting bandwidths up to ~80 MHz per channel. DDR LVDS outputs stream the digitized I/Q into FPGAs running demodulation algorithms, and the SPI port lets the FPGA reconfigure gain and channel selection on the fly. The exposed-pad QFN provides a low-thermal-resistance footprint for dense SDR board layouts.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para LTC2155IUP-12 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | LTC2155CUP-12 | LTC2155IUP-14 | LTC2156IUP-12 | LTC2157IUP-12 | LTC2155IUP-10 | AD9268XCPZ-125 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-pin QFN (9x9 mm) | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin LFCSP (QFN equivalent) - same footprint |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits | 10 bits | 16 bits |
| Sample Rate | 170 Msps | 170 Msps | 170 Msps | 210 Msps | 250 Msps | 170 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Supply Voltage | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
Diferenciadores clave
- Pin-compatible family spanning 12-/14-bit resolution and 170-250 Msps (frente a Single-channel 16-bit AD9268XCPZ-125)
- Dual simultaneous sampling at 170 Msps with 1.25 GHz analog bandwidth (frente a Single-channel AD9268XCPZ-125)
- Industrial -40 C to +85 C operating range for harsh-environment deployment (frente a LTC2155CUP-12 commercial variant)
Notas de diseño
The LTC2155IUP-12's exposed thermal pad must be soldered to a continuous, unbroken ground plane on the top PCB layer to provide both thermal dissipation (~28 C/W theta_JA) and a low-impedance signal return for the differential analog inputs and DDR LVDS outputs. Use multiple stitching vias (8-12 recommended) directly under the pad to tie it to internal ground planes. Route the differential analog inputs (AIN1+/AIN1-, AIN2+/AIN2-) as length-matched 100-ohm differential transmission lines with ground-side reference, and keep the 1.8V analog supply (AVDD) and output-driver supply (OVDD) separated by ferrite beads to prevent digital switching noise from coupling into the analog front end.
Do not exceed the 1.8V AVDD/OVDD supply absolute maximum of 2.0V, or the device will suffer permanent damage. Always enable the clock (CLK+/CLK-) before applying the analog input signals to avoid saturation. The DDR LVDS outputs require a 100-ohm differential termination resistor placed close to the receiver; omitting this termination degrades signal integrity and increases EMI. The SPI configuration port (CS/SCK/SDI/SDO) must be held stable or properly terminated during power-up to prevent the part from entering an unintended test mode.
Estimated: With 1.5 Vp-p differential inputs and 170 Msps clock, the analog input edge rates demand matched 100-ohm differential routing (Zo = 100 ohm +/-10%) on a controlled-impedance stackup. Keep analog input trace length below 1/10 of the wavelength at the input's highest significant frequency (e.g., for 500 MHz IF inputs, keep traces under 6 mm) and surround them with ground both. Place the input common-mode (VCM) decoupling capacitor as close to the AIN pins as possible to reduce common-mode noise pickup.
Información de cumplimiento
RoHS/REACH compliance indicated by #PBF suffix per Analog Devices ordering information. Not AEC-Q100 qualified - contact Analog Devices automotive product group for qualified alternatives.
