LTC2155IUP-12 - Dual 12-Bit 170Msps ADC, 1.8V, 64-QFN | Analog Devices
料号： LTC2155IUP-12 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $62.52 | $62.52 |
| 10 | $59.4 | $594.00 |
| 100 | $56.27 | $5,627.00 |
| 500 | $53.14 | $26,570.00 |
| 1,000 | $50.02 | $50,020.00 |
LTC2155IUP-12 概述
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. Pipelined ADCs use a multi-stage architecture that enables high sampling rates while maintaining moderate resolution and low power. The LTC2155 belongs to the pipelined ADC sub-family of data converters, which sits within the broader category of mixed-signal ICs and signal-chain components.
Key features of the LTC2155-12 family include DDR LVDS outputs for low-noise high-speed data transfer, an optional sample-and-hold front end, a clock duty-cycle stabilizer for jitter-tolerant sampling, and low-power Sleep and Nap modes. The 1.25 GHz full-power input bandwidth allows direct sampling of IF signals. A serial SPI port provides flexible configuration of output modes, gain, and channel selection.
The 1.8V single-supply operation simplifies power-tree design in FPGA or ASIC co-located systems, while DDR LVDS outputs minimize pin count and reduce EMI by carrying data on differential edges. The pipelined core uses calibrated capacitor arrays and shared references between channels to keep channel-to-channel gain and offset matching tight.
Typical applications include communications receivers (LTE/3G/4G base-station digitizers), radar and phased-array antenna IF sampling, broadband test-and-measurement instrumentation, medical imaging front-ends, and high-speed data acquisition systems. The wide input bandwidth also suits digital oscilloscope front-end channels. The pin-compatible 14-bit (LTC2155-14) and lower-speed family members provide upgrade and cost-down paths on the same PCB footprint.
When designing with this device, route the differential analog inputs as length-matched 100-ohm transmission lines, keep the 1.8V analog supply isolated from noisy digital rails, and place the SPI configuration traces away from the LVDS output edges. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and signal-return integrity.
This page synthesizes distributor pricing, family upgrade/downgrade alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： LTC2155IUP-12 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2155IUP-12 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature Range, RoHS Status, Number of Channels, Resolution.
快速对比工具——选择替代料号进行并排对比：
LTC2155CUP-12
✅ 直接替换✓ 有现货
$44.25 / 个
查看数据手册 →LTC2155IUP-14
✅ 直接替换✓ 有现货
$107.04 / 个
查看数据手册 →LTC2156IUP-12
✅ 直接替换📋 参考替代料（不在目录中）
LTC2157IUP-12
✅ 直接替换✓ 有现货
$64.89 / 个
查看数据手册 →LTC2155IUP-10
✅ 直接替换📋 参考替代料（不在目录中）
AD9268XCPZ-125
✅ 直接替换✓ 有现货
$30.95 / 个
查看数据手册 →LTC2155IUP-12 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 170 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| 输入电压范围 | 1.5 Vp-p |
| Full-Power Bandwidth | 1.25 GHz |
| SNR | 68.5 dB |
| SFDR | 90 dB |
| 电源电压 | 1.8 V (single) |
| Total Power Dissipation | 545 mW |
| Output Interface | DDR LVDS |
| Configuration Interface | Serial SPI port |
| 工作温度范围 | -40 C to +85 C (industrial) |
| 封装 | 64-pin QFN (9x9 mm) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (#PBF suffix) |
LTC2155IUP-12 引脚配置
| 引脚 1 | AIN1+ — Channel 1 differential analog input positive |
| 引脚 2 | AIN1- — Channel 1 differential analog input negative |
| 引脚 3 | SENSE — Reference configuration pin |
| 引脚 4 | GND — Ground (must tie to exposed pad) |
| 引脚 5 | VCM — Common-mode voltage output |
| 引脚 6 | VREF — Reference voltage decoupling |
| 引脚 7 | AIN2+ — Channel 2 differential analog input positive |
| 引脚 8 | AIN2- — Channel 2 differential analog input negative |
| 引脚 9 | GND — Ground |
| 引脚 10 | CLK+ — Differential sample clock positive |
| 引脚 11 | CLK- — Differential sample clock negative |
| 引脚 12 | OGND — Output driver ground |
| 引脚 13 | OVDD — Output driver 1.8V supply |
| 引脚 14 | OUT1A+ — Channel 1 DDR LVDS output A positive |
| 引脚 15 | OUT1A- — Channel 1 DDR LVDS output A negative |
| 引脚 16 | OUT1B+ — Channel 1 DDR LVDS output B positive |
| 引脚 17 | OUT1B- — Channel 1 DDR LVDS output B negative |
| 引脚 18 | OUT2A+ — Channel 2 DDR LVDS output A positive |
| 引脚 19 | OUT2A- — Channel 2 DDR LVDS output A negative |
| 引脚 20 | OUT2B+ — Channel 2 DDR LVDS output B positive |
| 引脚 21 | OUT2B- — Channel 2 DDR LVDS output B negative |
| 引脚 22 | OGND — Output driver ground |
| 引脚 23 | DCO+ — DDR LVDS data clock output positive |
| 引脚 24 | DCO- — DDR LVDS data clock output negative |
| 引脚 25 | FCO+ — DDR LVDS frame clock output positive |
| 引脚 26 | FCO- — DDR LVDS frame clock output negative |
| 引脚 27 | OGND — Output driver ground |
| 引脚 28 | OVDD — Output driver 1.8V supply |
| 引脚 29 | CS — SPI chip select (active low) |
| 引脚 30 | SCK — SPI serial clock |
| 引脚 31 | SDI — SPI serial data input |
| 引脚 32 | SDO — SPI serial data output |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | NC — Not connected (per datasheet) |
| 引脚 35 | MODE — Mode select strap |
| 引脚 36 | OGND — Output driver ground |
| 引脚 37 | AVDD — Analog 1.8V supply |
| 引脚 38 | AVDD — Analog 1.8V supply |
| 引脚 39 | GND — Ground |
| 引脚 40 | AVDD — Analog 1.8V supply |
| 引脚 41 | GND — Ground |
| 引脚 42 | AVDD — Analog 1.8V supply |
| 引脚 43 | GND — Ground |
| 引脚 44 | AVDD — Analog 1.8V supply |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | GND — Ground |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
| 引脚 49 | GND — Ground |
| 引脚 50 | NC — Not connected (per datasheet) |
| 引脚 51 | GND — Ground |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | GND — Ground |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | GND — Ground |
| 引脚 56 | NC — Not connected (per datasheet) |
| 引脚 57 | GND — Ground |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | GND — Ground |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | AVDD — Analog 1.8V supply |
| 引脚 62 | GND — Ground |
| 引脚 63 | AVDD — Analog 1.8V supply |
| 引脚 64 | GND — Ground |
典型应用
LTC2155IUP-12 适用于 6 应用s: Communications Receiver IF Sampling, Radar and Phased-Array Antenna Front-End, Broadband Test and Measurement Instrumentation, Medical Imaging Front-End Digitizer, High-Speed Data Acquisition Systems, Software Defined Radio (SDR) Baseband.
Communications Receiver IF Sampling
The LTC2155IUP-12 suits multi-carrier communications receiver IF-stage digitizers because its dual channels simultaneously sample I/Q or diversity paths at 170 Msps, and the 1.25 GHz full-power bandwidth lets it capture IF frequencies up to ~500 MHz without aliasing. With 90 dB SFDR the converter preserves modulation fidelity for LTE, 4G, and emerging 5G NR signal chains, while DDR LVDS outputs drive directly into FPGAs without level translation.
推荐
Radar and Phased-Array Antenna Front-End
In radar and phased-array antenna systems the LTC2155IUP-12's dual simultaneous-sampling channels preserve channel-to-channel phase coherence across antenna elements. Its 1.25 GHz analog input bandwidth supports direct IF sampling at L-band and S-band radar IF frequencies, while 68.5 dB SNR / 90 dB SFDR maintains target detection sensitivity and dynamic range. Pin-compatible 14-bit variants allow upgrade to higher dynamic range without PCB rework.
推荐
Broadband Test and Measurement Instrumentation
Test and measurement instruments such as digital oscilloscopes, spectrum analyzers, and signal analyzers use the LTC2155IUP-12 as an input-channel digitizer because its dual channels, 170 Msps real-time sample rate, and 1.25 GHz analog input bandwidth cover bandwidths beyond 100 MHz on each channel. The SPI configuration port allows gain and offset calibration per channel, and DDR LVDS outputs minimize the FPGA pin count required to capture high-speed data streams.
推荐
Medical Imaging Front-End Digitizer
Ultrasound and other medical imaging front-ends use the LTC2155IUP-12 because its dual simultaneous sampling captures phased-array transducer channels with precise inter-channel timing. Low power (545 mW total) simplifies thermal management in cart-based portable ultrasound systems, while the 1.8V single supply eases battery-powered operation. The wide input bandwidth supports direct sampling of RF-modulated transducer signals before beamforming.
推荐
High-Speed Data Acquisition Systems
Industrial and laboratory data acquisition systems use the LTC2155IUP-12 as a dual-channel simultaneous-sampling digitizer with high dynamic range. The pipelined core delivers low-latency conversions suitable for closed-loop control and event-triggered capture, while the SPI port enables per-channel gain, offset, and channel-selection adjustments. Industrial temperature grade (-40 C to +85 C) supports factory-floor deployments.
推荐
Software Defined Radio (SDR) Baseband
Software defined radio platforms use the LTC2155IUP-12 as a baseband or low-IF digitizer because the dual channels directly capture I/Q signal pairs at 170 Msps, supporting bandwidths up to ~80 MHz per channel. DDR LVDS outputs stream the digitized I/Q into FPGAs running demodulation algorithms, and the SPI port lets the FPGA reconfigure gain and channel selection on the fly. The exposed-pad QFN provides a low-thermal-resistance footprint for dense SDR board layouts.
推荐
推荐产品汇总
工程参考数据： LTC2155IUP-12 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2155CUP-12 | LTC2155IUP-14 | LTC2156IUP-12 | LTC2157IUP-12 | LTC2155IUP-10 | AD9268XCPZ-125 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-pin QFN (9x9 mm) | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin LFCSP (QFN equivalent) - same footprint |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits | 10 bits | 16 bits |
| Sample Rate | 170 Msps | 170 Msps | 170 Msps | 210 Msps | 250 Msps | 170 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Supply Voltage | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
关键差异点
- Pin-compatible family spanning 12-/14-bit resolution and 170-250 Msps （对比 Single-channel 16-bit AD9268XCPZ-125)
- Dual simultaneous sampling at 170 Msps with 1.25 GHz analog bandwidth （对比 Single-channel AD9268XCPZ-125)
- Industrial -40 C to +85 C operating range for harsh-environment deployment （对比 LTC2155CUP-12 commercial variant)
设计说明
The LTC2155IUP-12's exposed thermal pad must be soldered to a continuous, unbroken ground plane on the top PCB layer to provide both thermal dissipation (~28 C/W theta_JA) and a low-impedance signal return for the differential analog inputs and DDR LVDS outputs. Use multiple stitching vias (8-12 recommended) directly under the pad to tie it to internal ground planes. Route the differential analog inputs (AIN1+/AIN1-, AIN2+/AIN2-) as length-matched 100-ohm differential transmission lines with ground-side reference, and keep the 1.8V analog supply (AVDD) and output-driver supply (OVDD) separated by ferrite beads to prevent digital switching noise from coupling into the analog front end.
Do not exceed the 1.8V AVDD/OVDD supply absolute maximum of 2.0V, or the device will suffer permanent damage. Always enable the clock (CLK+/CLK-) before applying the analog input signals to avoid saturation. The DDR LVDS outputs require a 100-ohm differential termination resistor placed close to the receiver; omitting this termination degrades signal integrity and increases EMI. The SPI configuration port (CS/SCK/SDI/SDO) must be held stable or properly terminated during power-up to prevent the part from entering an unintended test mode.
Estimated: With 1.5 Vp-p differential inputs and 170 Msps clock, the analog input edge rates demand matched 100-ohm differential routing (Zo = 100 ohm +/-10%) on a controlled-impedance stackup. Keep analog input trace length below 1/10 of the wavelength at the input's highest significant frequency (e.g., for 500 MHz IF inputs, keep traces under 6 mm) and surround them with ground both. Place the input common-mode (VCM) decoupling capacitor as close to the AIN pins as possible to reduce common-mode noise pickup.
合规信息
RoHS/REACH compliance indicated by #PBF suffix per Analog Devices ordering information. Not AEC-Q100 qualified - contact Analog Devices automotive product group for qualified alternatives.
