PI7C9X3G606GP - PCIe Gen3 6-Port Packet Switch | Diodes Inc.
N.º de pieza: PI7C9X3G606GP ✓ Activo| Cant. | Precio unitario | Total |
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| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
| 100 | $0 | $0,00 |
| 500 | $0 | $0,00 |
| 1.000 | $0 | $0,00 |
PI7C9X3G606GP Descripción general
A PCIe packet switch is an interface bridge device in the PCI Express fabric hierarchy that connects a single root complex upstream port to one or more downstream ports, providing address translation, packet routing, and hot-plug management. Within the interface IC family hierarchy, the PI7C9X3G606GP belongs to the PCIe switch category of interface ICs, sitting above PCIe retimers and below full root complex devices. Packet switches are fundamental building blocks in storage controllers, network line cards, and multi-host server systems where PCIe lanes must be fan-out or fan-in aggregated.
Key features of the PI7C9X3G606GP include six lanes of PCIe Gen3 SERDES operating at 8 GT/s per lane, flexible lane-width allocation per port, and support for upstream port, downstream port, and cross-link port types. GreenPacket Technology reduces power consumption during low-activity periods, a significant benefit for power-sensitive embedded and edge platforms. Sideband management signals and an I2C interface provide configuration and control paths for system bring-up and runtime management.
Architecturally, the device allows the flexible port configuration by allocating variable lane widths for each port, so a single 6-lane SERDES pool can be partitioned to match the exact topology required - for example, x2 upstream plus two x2 downstream ports. According to the manufacturer datasheet, the packet switch can be configured to have different port types such as upstream port, downstream ports, and cross-link, giving system designers topology freedom without changing silicon.
Typical applications include NVMe SSD expansion in storage systems, multi-host PCIe fan-out in server and network appliances, and industrial embedded systems that aggregate several endpoint devices onto one host root port. The device is a natural fit for storage and network systems that require flexible lane configuration at Gen3 data rates.
When designing with this device, verify the sideband management signal definitions (including the EECK pin) against the latest datasheet revision 2, dated 11/02/2023, which updated sideband management signals, power-up sequencing, and power consumption tables.
This page synthesizes verified distributor data, package information, practical design notes, and drop-in alternative options not consolidated in the manufacturer datasheet alone.
Alternativas directas para PI7C9X3G606GP — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
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PI7C9X3G606GPBFCAEX
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PI7C9X3G606GPAQ3FCAEX
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PI7C9X3G1632GP
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PI7C9X3G606GP Valores máximos y características eléctricas
| Product Type | PCI Express Gen3 Packet Switch |
| Number of Ports | 6-port (flexible 3-port, 5-port, and 6-port configurations) |
| Number of Lanes | 6 lanes |
| PCIe Generation | Gen3 (8 GT/s per lane) |
| Port Types Supported | Upstream port, downstream ports, cross-link |
| Lane Width Allocation | Variable lane widths per port (flexible) |
| Special Technology | GreenPacket Technology (power saving) |
| Sideband Management | Sideband management signals incl. EECK pin |
| Configuration Interface | I2C interface |
| Encapsulado | 144-ball FC-LFBGA (10x10 mm) |
| Tipo de montaje | Surface Mount |
| Packaging | Tape & Reel, 3K (per ordering code PI7C9X3G606GPBFCAEX) |
| Manufacturer | Diodes Incorporated |
| Datasheet Revision | Rev 2, dated 11/02/2023 (initial release 03/08/2021) |
Guía de configuración de pines de PI7C9X3G606GP 144-ball fc-lfbga (10x10 mm)
Configuración de pines para PI7C9X3G606GP (encapsulado 144-ball fc-lfbga (10x10 mm)). Este dispositivo de potencia presenta terminales de puerta, drenador y fuente. Para encapsulados no polarizados, consulte la hoja de datos del fabricante para conocer la orientación exacta del pin 1 y los detalles del footprint. Las aplicaciones habituales incluyen el diseño de fuentes de alimentación, el accionamiento de motores y la conmutación de cargas.
No hay datos detallados de patillaje disponibles para PI7C9X3G606GP.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
PI7C9X3G606GP es adecuado para 6 aplicacións: NVMe SSD Storage Expansion, Server and Network Line Card Fan-Out, Industrial Embedded Systems, Multi-Host Storage Access Systems, Edge AI and Accelerator Modules, Test, Measurement and Prototyping.
NVMe SSD Storage Expansion
The PI7C9X3G606GP fits NVMe storage expansion because its six PCIe Gen3 lanes at 8 GT/s per lane match NVMe SSD host interface rates, and its variable lane-width allocation lets one switch fan a single host root port out to multiple M.2 or U.2 SSD endpoints. In a typical x2-upstream plus two x2-downstream partition, the switch adds minimal latency while GreenPacket Technology cuts power when SSD links sit idle - valuable in fanless NAS and edge storage appliances. Place the switch close to the SSD connectors to keep Gen3 trace lengths within channel budget, and use the I2C interface for SKU-dependent port strapping at manufacturing test.
Recomendado
Server and Network Line Card Fan-Out
In server and network appliances, the PI7C9X3G606GP aggregates multiple NIC, accelerator, or control-fabric endpoints onto a single root port. Its flexible 3-port, 5-port, and 6-port topologies let one board design serve several SKUs simply by changing lane partitioning rather than swapping silicon. The cross-link port type supports multi-host backplane designs where two hosts share downstream resources. The updated sideband management and power-up sequencing documentation in datasheet Rev 2 simplifies hot-plug and reset design for line-card serviceability. For higher-density blades needing more than six lanes, move up the family to the 32-lane PI7C9X3G1632GP.
Recomendado
Industrial Embedded Systems
Industrial controllers, machine-vision frames, and test modules frequently need to connect several PCIe endpoints - frame grabbers, FPGA cards, motion controllers - to one embedded host. The PI7C9X3G606GP fits these designs because its 10x10 mm 144-ball FC-LFBGA conserves board area in conduction-cooled enclosures, while GreenPacket Technology lowers average system power for passively cooled installations. The I2C configuration interface supports in-field topology reconfiguration and diagnostics, and the sideband management signals integrate with PLC-style reset supervision. According to the manufacturer, the flexible lane allocation enables one carrier board design to host multiple module combinations without hardware change.
Recomendado
Multi-Host Storage Access Systems
The cross-link port capability of the PI7C9X3G606GP enables multi-host topologies where two root complexes each reach shared NVMe storage - a common pattern in high-availability appliances and failover storage nodes. The switch partitions its six Gen3 lanes flexibly between hosts and shared downstream ports, and the packet-switch fabric handles address translation between domains. In this role the device reduces the component count versus discrete multiplexer approaches, and the power-up sequencing documented in Figure 10-1 of datasheet Rev 2 defines a deterministic bring-up order for dual-domain designs. Verify domain isolation requirements against your storage failover software stack.
Recomendado
Edge AI and Accelerator Modules
Edge AI modules pair an SoC with one or two NPUs or inference accelerators over PCIe. The PI7C9X3G606GP suits these designs when the SoC exposes a single x4 Gen3 root port that must serve an accelerator plus a companion device such as a 10GbE MAC or capture FPGA: the switch splits lanes to match each endpoint's bandwidth need, avoiding overprovisioning. Gen3 8 GT/s keeps accelerator-host links off the critical path for most inference workloads, while GreenPacket Technology supports duty-cycled inference profiles typical of battery- or PoE-powered edge nodes. Compact 144-ball footprint eases integration on 60-90 mm SO-DIMM-style modules.
Recomendado
Test, Measurement and Prototyping
Bench validation of PCIe Gen3 endpoints benefits from a configurable host-side fabric element, and the PI7C9X3G606GP serves as that element in custom test carriers. Engineers use the I2C interface to script lane-width and port-type changes during characterization, exercising endpoints under different topology configurations from one fixture. The updated link status register map (Section 9.3.47 in Rev 2) supports automated link-state polling in test software. Because the 3-port and 6-port partitions coexist in the same silicon, test engineering can qualify multiple product SKUs on a single switch-based carrier board, reducing fixture cost and qualification cycle time.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para PI7C9X3G606GP — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | PI7C9X3G606GPBFCAEX | PI7C9X3G606GPAQ3FCAEX | PI7C9X3G1632GP |
|---|---|---|---|---|
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| PCIe Lanes | 6 lanes, Gen3 (8 GT/s) | 6 lanes, Gen3 | 6 lanes, Gen3 | 32 lanes, Gen3 |
| Port Count / Configurations | 6 ports; 3/5/6-port flexible configs | Identical (same die) | Identical (same die) | 16 ports / 32 lanes |
Diferenciadores clave
- Flexible 3/5/6-port configurations from one die (frente a PI7C9X3G1632GP)
- GreenPacket Technology power saving (frente a Generic discrete fan-out approaches)
- Cross-link port support for multi-host designs (frente a PI7C9X3G606GPBFCAEX (identical) / fixed-fabric alternatives)
Notas de diseño
Follow the initial power-up sequence in Figure 10-1 of datasheet Rev 2 (11/02/2023) exactly: PCIe packet switches require correct rail sequencing and strap-sample timing before the 100/200 MHz reference clock stabilizes, otherwise the upstream link may train at degraded widths. Review the updated Table 12-12 power consumption figures for your lane-width partition to size core and auxiliary rails; estimated: budget worst case using the datasheet maximum values, not typical, when designing shared regulators with other Gen3 silicon.
Gen3 SERDES at 8 GT/s leaves little insertion-loss margin: keep FC-LFBGA breakout stubs short, route differential pairs to 85-ohm (estimated nominal for PCIe) with length matching within specification for Gen3 channels, and place AC coupling capacitors per datasheet layout guidance. If downstream links run to slots or cables longer than the Gen3 channel budget, consider a family-scaled switch or retimer rather than pushing marginal traces. Use the sideband management signals (including the EECK pin defined in updated Section 3.5) with proper pull resistors - floating sideband inputs are a common bring-up failure mode.
Use the latest datasheet Rev 2 (11/02/2023), not the 03/08/2021 initial release: Rev 2 added thermal data with heat spreader to Table 13-1, revised sideband management signals for EECK, updated the power-up sequence, power consumption, I2C interface (Section 5.4), and link status register (Section 9.3.47). Designs based on Rev 1 may misstrap EECK or sequence rails incorrectly. Also note PI7C9X3G606GPBFCAEX is the purchasable ordering code (Tape & Reel 3K); the bare base MPN may not map to a stocked line item at distributors.
Información de cumplimiento
Compliance data was not present in the verified web data. Consult the Diodes Incorporated product page (https://www.diodes.com/part/view/PI7C9X3G606GP) and datasheet for current RoHS/REACH declarations.
