RTQ2533WGQV(2) - 3A Ultra-Low Noise LDO, 6.5V, VQFN-20 | Richtek
N.º de pieza: RTQ2533WGQV(2) ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $1.85 | $1,85 |
| 10 | $1.67 | $16,70 |
| 100 | $1.48 | $148,00 |
| 500 | $1.32 | $660,00 |
| 1.000 | $1.18 | $1.180,00 |
| 3.000 | $1.05 | $3.150,00 |
RTQ2533WGQV(2) Descripción general
An LDO (Low-Dropout) linear regulator is a type of linear voltage regulator that maintains a regulated output voltage even when the input-to-output differential approaches the minimum pass-element headroom. Within the broader product hierarchy, an LDO is a linear regulator is a voltage regulator is a power management IC. Because the pass element operates in the linear region (not switching), the LDO adds no high-frequency switching noise to the output - this is the defining advantage over switch-mode converters for noise-sensitive analog and RF rails.
Key features of the RTQ2533WGQV(2) include pin-programmable output voltage that eliminates feedback resistors for the most common voltages (reducing BOM count and PCB area), an exposed thermal pad for high-current operation, internal soft-start to limit inrush current, and built-in protection including current limit and thermal shutdown. The combination of 3 A continuous load and 180 mV maximum dropout supports tight point-of-load regulation in systems where headroom is constrained.
The regulator uses a PNP pass architecture with a precision bandgap reference and trimmed feedback network, achieving 1% output accuracy across the entire VIN/VOUT/load/temperature envelope. The exposed thermal pad on the VQFN-20 package provides a low thermal-resistance path (theta_JC substantially lower than theta_JA) for sustained 3 A operation without external heatsinking.
Typical applications include FPGA and ASIC core/IO rail regulation, server and networking point-of-load supplies, audio codec and DAC power rails, RF transceiver local regulation, and industrial 5 V/3.3 V point-of-load conversion. The wide input range and 3 A output suit multi-rail systems where one input rail feeds several regulated outputs.
When designing with this part, follow the manufacturer's PCB layout guidelines: place input and output capacitors as close as possible to the IC, use sufficient copper pour on the exposed thermal pad to keep junction temperature below 125 C, and select the output voltage via proper PCB routing as documented in the datasheet to avoid needing external resistors.
This page synthesizes distributor pricing, drop-in Richtek same-family alternatives, and practical thermal/layout guidance not consolidated in the manufacturer datasheet alone, giving engineers a single source for selection and procurement decisions.
Alternativas directas para RTQ2533WGQV(2) — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
RTQ2533WGQV
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
RTQ2533W
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
RTQ2533AGQV
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
RTQ2533WGQV(2) Valores máximos y características eléctricas
| Topología | Low-Dropout (LDO) Linear Regulator |
| Rango de tensión de entrada | 1.1 V to 6.5 V |
| Output Voltage Range (set by resistive divider) | 0.8 V to 5.5 V |
| Output Voltage Range (set by PCB layout) | 0.8 V to 3.95 V |
| Corriente de salida máxima | 3 A |
| Tensión de dropout | 180 mV (max at 3 A) |
| Output Noise (0.8 V) | 6.8 uVrms |
| Output Noise (3.3 V) | 10 uVrms |
| PSRR | 40 dB at 500 kHz |
| Output Voltage Accuracy | 1% over line, load, and temperature |
| Tipo de salida | Positive Adjustable (pin-selectable) |
| Encapsulado | 20-VQFN (3.5 mm x 3.5 mm) |
| Tipo de montaje | Surface Mount |
| Thermal Protection | Thermal Shutdown |
Configuración de pines de RTQ2533WGQV(2)
| Pin 1 | VIN — Input voltage supply |
| Pin 2 | VIN — Input voltage supply |
| Pin 3 | NC — Not connected (per datasheet) |
| Pin 4 | EN — Enable (active high) |
| Pin 5 | NC — Not connected (per datasheet) |
| Pin 6 | VSET — Voltage set pin (pin-selectable output) |
| Pin 7 | NC — Not connected (per datasheet) |
| Pin 8 | ADJ/FB — Adjust/feedback (for resistive divider mode) |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | PG — Power good indicator |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | VOUT — Regulated output voltage |
| Pin 14 | VOUT — Regulated output voltage |
| Pin 15 | VOUT — Regulated output voltage |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | GND — Ground |
| Pin 18 | GND — Ground |
| Pin 19 | GND — Ground (thermal pad region) |
| Pin 20 | GND — Ground (exposed thermal pad) |
Aplicaciones típicas
RTQ2533WGQV(2) es adecuado para 6 aplicacións: FPGA Core/IO Point-of-Load Regulation, Server and Networking 5 V/3.3 V POL Conversion, Audio Codec / DAC Power Rail, RF Transceiver Local Regulation, Industrial 3.3 V/5 V Point-of-Load, USB-Powered Single-Cell Li-Ion Device.
FPGA Core/IO Point-of-Load Regulation
The RTQ2533WGQV(2) provides clean point-of-load regulation for FPGA core (0.85 V) and IO (1.8 V/3.3 V) rails. The 3 A continuous current from a 3.3 V or 5 V input bus supports multi-rail FPGA designs where each voltage domain needs a dedicated regulator; pin-selectable output up to 3.95 V eliminates feedback resistors for standard FPGA voltages. Ultra-low noise of 10 uVrms at 3.3 V preserves FPGA PLL supply integrity and minimizes jitter on high-speed transceivers; the 40 dB PSRR at 500 kHz attenuates residual ripple from upstream buck converters. Place the device between the intermediate bus and the FPGA decoupling network, using 22 uF ceramic input/output caps per Richtek EVB UG2533WGQV2.
Recomendado
Server and Networking 5 V/3.3 V POL Conversion
The RTQ2533WGQV(2) converts a 5 V or 3.3 V intermediate bus into tightly regulated lower-voltage rails for server and networking ASICs. The 6.5 V maximum input accepts 5 V system buses directly, and 3 A output handles multi-rail SoC loads. Its pin-selectable outputs (0.8 V to 3.95 V) cover common networking voltages (1.0 V, 1.2 V, 1.8 V, 2.5 V) without external feedback components, simplifying BOM. Compared with a buck converter, the linear topology adds no switching noise to the ASIC's sensitive clocking and SERDES analog domains - critical for maintaining BER margins on 10G/25G Ethernet links.
Recomendado
Audio Codec / DAC Power Rail
The RTQ2533WGQV(2) supplies low-noise power for audio codecs and DACs where power rail noise directly impacts dynamic range. Its 6.8 uVrms output noise at 0.8 V and 10 uVrms at 3.3 V are well below the audibility threshold of common codec PSRR designs, ensuring clean analog domain supply. The 3 A capability supports higher-power Class-D amplifier front-end rails in multi-channel audio systems. Combined with the 1% accuracy over line/load/temperature, the part maintains channel-to-channel gain matching. Use it as a post-buck-rail LDO with input LC filter to suppress upstream switching ripple from 50 kHz to 1 MHz.
Recomendado
RF Transceiver Local Regulation
The RTQ2533WGQV(2) provides local regulation for RF transceivers' VCO, PLL, and PA-pre-driver rails where supply noise modulates phase and creates spurs. Its 40 dB PSRR at 500 kHz attenuates residual switching noise from upstream converters that would otherwise appear as phase-noise sidebands or reference spurs. The 3 A continuous current handles transmit-path pre-driver loads in compact RF modules. The exposed thermal pad on VQFN-20 (3.5x3.5 mm) supports sustained current without external heatsinking, valuable in size-constrained radio designs.
Recomendado
Industrial 3.3 V/5 V Point-of-Load
The RTQ2533WGQV(2) delivers 3 A from industrial 24 V buck-converter intermediate rails or 5 V system buses into tightly regulated 3.3 V, 2.5 V, 1.8 V, or 1.2 V supplies for industrial controllers and PLCs. The wide 1.1-6.5 V input accommodates a 3.3 V pre-regulated rail or a 5 V USB-input design, and pin-selectable output reduces BOM for high-volume industrial products. The exposed thermal pad and -40 C to +125 C operating range (per Richtek datasheet) support industrial temperature environments. Internal current limit and thermal shutdown provide field-protection against output short circuits.
Recomendado
USB-Powered Single-Cell Li-Ion Device
The RTQ2533WGQV(2) regulates directly from a single Li-ion cell (3.0 V to 4.2 V) or USB 5 V input into a 1.0 V to 3.3 V rail for portable SoCs and image sensors. The 1.1 V minimum input allows operation even when the Li-ion cell sags under heavy load, and 180 mV dropout supports up to 3 A from a near-depleted cell. The ultra-low 6.8 to 10 uVrms noise preserves CMOS image sensor SNR in low-light capture and avoids WiFi/BT module desensitization. Place upstream of the PMIC's LDO outputs in portable designs that need post-PMIC active filtering.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para RTQ2533WGQV(2) — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | RTQ2533WGQV | RTQ2533W | RTQ2533AGQV |
|---|---|---|---|---|
| Brand | Richtek | Richtek | Richtek | Richtek |
| Package | VQFN-20 (3.5x3.5) | VQFN-20 (3.5x3.5) - same | VQFN-20 (3.5x3.5) - same | VQFN-20 (3.5x3.5) - same |
| Input Voltage Range | 1.1 V to 6.5 V | 1.1 V to 6.5 V | 1.1 V to 6.5 V | 1.1 V to 6.5 V |
| Output Current | 3 A | 3 A | 3 A | 3 A |
| Output Voltage Range | 0.8 V to 5.5 V (resistive) / 0.8 V to 3.95 V (pin-select) | 0.8 V to 5.5 V (resistive) / 0.8 V to 3.95 V (pin-select) | 0.8 V to 5.5 V (resistive) / 0.8 V to 3.95 V (pin-select) | 0.8 V to 5.5 V (resistive) / 0.8 V to 3.95 V (pin-select) |
| Dropout Voltage (max) | 180 mV at 3 A | 180 mV at 3 A | 180 mV at 3 A | 180 mV at 3 A |
| Output Noise (3.3 V) | 10 uVrms | 10 uVrms | 10 uVrms | 10 uVrms |
| PSRR at 500 kHz | 40 dB | 40 dB | 40 dB | 40 dB |
Diferenciadores clave
- Pin-selectable output up to 3.95 V without external resistors (frente a Standard LDOs requiring feedback resistor divider)
- 3 A continuous output in compact 3.5x3.5 mm VQFN-20 (frente a Comparable 3 A LDOs in larger packages (e.g., SOIC-8 exposed pad or 5x5 mm QFN))
- Ultra-low 6.8 uVrms output noise at 0.8 V (frente a Generic 3 A LDOs with 50-100 uVrms output noise)
Notas de diseño
Estimated thermal analysis: at VIN=5 V, VOUT=3.3 V, and 3 A load, the part dissipates approximately 5.1 W. The VQFN-20 (3.5x3.5 mm) package requires substantial PCB copper pour on the exposed thermal pad (at least 1 square inch on top and bottom layers with thermal vias) to maintain junction temperature below 125 C. Without thermal management, derate to 1.5 A to 2 A or use a smaller VIN-VOUT differential. Reference Richtek EVB UG2533WGQV2 for the recommended thermal layout.
Place input and output ceramic capacitors as close as possible to the IC pins (within 1-2 mm). Use a low-ESR 22 uF X7R ceramic on the input and a 22 uF X7R ceramic on the output per the Richtek reference design. Add a 0.1 uF bypass cap in parallel for high-frequency decoupling. The exposed thermal pad must be soldered to a continuous ground copper plane with thermal vias for heat extraction.
When using pin-selectable output mode (0.8 V to 3.95 V without external resistors), the VSET pin must be tied to the correct voltage according to the datasheet's pin-programming table - floating or mis-wiring VSET results in undefined output voltage or output voltage out of regulation. When using the resistive divider mode for 0.8 V to 5.5 V output, use 1% tolerance resistors for VOUT accuracy. Do not exceed the absolute maximum input voltage of 6.5 V; the part has no input TVS protection.
Información de cumplimiento
All compliance values inferred from 'Lead-Free and Green' classification on Richtek product page; [DATA_NEEDED] for REACH/AEC-Q100 formal documentation. Standard commercial-grade part; not automotive-qualified.
