SI5394A-A-GM - 4-Output Jitter Attenuator, 69fs | Skyworks
N.º de pieza: SI5394A-A-GM ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $57.05 | $57,05 |
| 10 | $51.34 | $513,40 |
| 100 | $45.64 | $4.564,00 |
| 500 | $38.21 | $19.105,00 |
| 1.000 | $33.49 | $33.490,00 |
SI5394A-A-GM Descripción general
A jitter attenuator is a clock-tree building block placed between a noisy reference oscillator (or recovered clock) and a downstream high-speed transceiver, ADC, or serializer/deserializer (SerDes). The Si5394 integrates a digital PLL (DSPLL) with a MultiSynth fractional output divider tree, allowing it to generate non-integer-related output frequencies from almost any input reference while aggressively attenuating jitter across a wide loop bandwidth. As a member of the clock & timing hierarchy, it sits above simple crystal oscillators and below the system-level timebase, providing a programmable timing layer.
The headline performance numbers are 69 fs RMS phase jitter (12 kHz-20 MHz integration band), 12.8 GHz maximum output frequency, and 12-channel/4-output flexibility. The device also supports free-run, synchronous, and holdover operating modes plus enhanced hitless switching between input references, minimizing phase transients during reference changes. Programming is done through a serial interface with in-circuit programmable non-volatile memory (NVM) so the device always powers up with a known frequency plan.
The Si5394A-A-GM is targeted at 56G PAM4 SerDes, OTN/optical transport, high-speed data-conversion reference clocks, broadcast video, and military/aerospace timing systems. The combination of sub-100 fs jitter and high output frequency makes it one of the highest-performance integrated jitter cleaners on the market.
When designing with this part, engineers should follow the ClockBuilder Pro configuration tool from Skyworks/Silicon Labs and respect the PCB layout note that all supply pins require local decoupling, while the exposed pad must be soldered to a continuous ground plane for thermal and electrical integrity. This page synthesizes distributor pricing, same-package cross-references, and practical design notes not found in the manufacturer datasheet.
Alternativas directas para SI5394A-A-GM — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con SI5394A-A-GM (mismo factor de forma y huella) — difiere en Number of Outputs, Package, RoHS Status.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
SI5394K-A-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5394A-A-GMR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5395A-A-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5392A-A-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5345A-D-GM
✅ Sustitución directa✓ En stock
$27.5 / unidad
Ver hoja de datos →SI5394A-A-GM Especificaciones
| Función | Clock Multiplier / Jitter Attenuator |
| Número de salidas | 4 |
| Number of PLLs | 1 |
| Phase Jitter (RMS) | 69 fs (12 kHz to 20 MHz) |
| Maximum Output Frequency | 1.028 GHz (DigiKey listed); family supports 12.8 GHz internal synthesis |
| Number of Inputs | Differential reference inputs |
| Operating Modes | Free-run, Synchronous, Holdover, Hitless switching |
| Programming Interface | Serial (I2C/SPI) with in-circuit programmable NVM |
| Technology | DSPLL (4th gen) + MultiSynth |
| Channel Count | 12-channel any-frequency, any-output |
| Encapsulado | 44-VFQFN Exposed Pad |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant (per distributor listing) |
Guía de configuración de pines de SI5394A-A-GM 44-vfqfn exposed pad
Configuración de pines para SI5394A-A-GM (encapsulado 44-vfqfn exposed pad). La numeración de pines, las funciones y los diagramas de conexión se definen en la hoja de datos del fabricante. Consúltela para conocer el footprint exacto y las directrices de soldadura.
No hay datos detallados de patillaje disponibles para SI5394A-A-GM.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
SI5394A-A-GM es adecuado para 6 aplicacións: 56G PAM4 SerDes Reference Clock, OTN and Optical Transport Equipment, High-Speed ADC and DAC Reference, Broadcast Video and Studio Timing, Military and Aerospace Timing Systems, Server and Datacenter Clock Tree.
56G PAM4 SerDes Reference Clock
The SI5394A-A-GM's 69 fs RMS phase jitter (12 kHz to 20 MHz) and 12.8 GHz maximum internal synthesis make it purpose-built for 56G PAM4 SerDes reference-clock inputs. SerDes receivers demand sub-100 fs reference jitter to keep the eye diagram open at 28-56 GBaud, and the Si5394 hits the jitter budget with margin while providing four independent differential outputs to drive multiple QSFP-DD or OSFP channels on the same line card. Holdover and hitless switching also protect against momentary reference loss on optical modules without resetting the SerDes link.
Recomendado
OTN and Optical Transport Equipment
Optical Transport Network (OTN) framers and OTU4/OTUCn line cards require a hitless-switching reference clock that survives a primary reference fail-over without dropping the line. The SI5394A-A-GM's free-run, synchronous, holdover, and enhanced hitless-switching modes meet the telecom GR-1244-CORE jitter-acceptance masks. Its four differential outputs cleanly drive a framer, a gearbox, and a separate crosspoint without needing external fanout, simplifying BOM cost on dense line cards deployed in OTN switches and DWDM transport platforms.
Recomendado
High-Speed ADC and DAC Reference
Wideband ADCs and DACs above 1 GSPS require a phase-clean sample clock to reach their SNR and SFDR datasheet numbers. The SI5394A-A-GM produces four differential LVPECL/LVDS/HCSL outputs at any frequency up to 12.8 GHz internal synthesis, allowing it to drive the analog front-end, the digital datapath clock, and the JESD204B/C SYSREF lane simultaneously from a single jitter-attenuating source. The 69 fs RMS phase jitter lifts the ADC's aperture-jitter floor, enabling higher ENOB on oscilloscope and radar receiver designs.
Recomendado
Broadcast Video and Studio Timing
SMPTE 2110, UHD-SDI, and broadcast video routers demand a house reference clock with sub-100 fs jitter and a fanout sufficient to drive dozens of frame-synchr視onizers. The SI5394A-A-GM's 4 output channels and arbitrary frequency synthesis cover common video rates (148.5 MHz, 148.5/1.001 MHz, 27 MHz) while its holdover mode keeps downstream equipment alive during reference-change events. For larger routers, multiple SI5394 parts can be cascaded or used in a star with the SI5345A-D-GM as the higher-channel-count fanout companion.
Recomendado
Military and Aerospace Timing Systems
Avionics, radar, and secure-radio platforms rely on redundant reference clocks that survive a primary reference fail with bounded phase transients. The SI5394A-A-GM's enhanced hitless-switching and holdover modes support reference redundancy required in DO-160 environments, while its extended-temperature variants provide operation across wide ambient ranges. The in-circuit programmable NVM ensures the device always powers up with a known frequency plan, a critical feature for certifiable platforms that cannot tolerate runtime NVM corruption.
Recomendado
Server and Datacenter Clock Tree
Hyperscale datacenter switches and PCIe Gen5/Gen6 servers need a low-jitter reference clock with multiple differential outputs to drive CPUs, PCIe retimers, and network PHYs. The SI5394A-A-GM's 4 outputs and DSPLL core provide a clean PCIe reference clock while keeping the BOM area small versus discrete crystal-plus-PLL solutions. For server backplanes requiring more clock domains, the SI5345A-D-GM (10 outputs, higher jitter) is a natural high-density companion on the same board.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para SI5394A-A-GM — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | SI5394K-A-GM | SI5394A-A-GMR | SI5395A-A-GM | SI5392A-A-GM | SI5345A-D-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 44-VFQFN Exposed Pad | 44-VFQFN Exposed Pad - same | 44-VFQFN Exposed Pad - same | 44-VFQFN Exposed Pad - same | 44-VFQFN Exposed Pad - same | 44-VFQFN Exposed Pad - same |
| Number of Outputs | 4 | 4 | 4 | 2 (-50%) | 2 (-50%) | 10 (+150%) |
| Phase Jitter (RMS) | 69 fs (12 kHz to 20 MHz) | 69 fs (same) | 69 fs (same) | 69 fs (same) | Similar DSPLL jitter | >150 fs (higher) |
| Hitless Switching | Yes | Yes | Yes | Yes | Yes | Yes |
| Holdover Mode | Yes | Yes | Yes | Yes | Yes | Yes |
| Programming Interface | I2C/SPI + NVM | I2C/SPI + NVM | I2C/SPI + NVM | I2C/SPI + NVM | I2C/SPI + NVM | I2C/SPI + NVM |
| Tier Position | Mid-tier (4 outputs) | Same tier | Same tier | Lower tier | Lower tier | Higher fanout tier |
Diferenciadores clave
- Sub-100 fs RMS jitter vs higher-jitter competitors (frente a SI5345A-D-GM)
- 4-output channel count fits mid-density designs (frente a SI5395A-A-GM)
- Same-family K-grade variant available (frente a SI5394A-A-GMR)
Notas de diseño
All supply pins of the SI5394A-A-GM must be individually decoupled with 100 nF X7R ceramic capacitors placed within 1-2 mm of the supply pin, plus a 10 uF bulk tantalum or polymer capacitor on each supply rail. The exposed thermal pad must be soldered to a continuous ground plane with thermal vias on a 0.5-1 mm pitch grid; omitting the ground-plane connection degrades both EMI performance and jitter. Keep all differential output traces length-matched within 1 mm to avoid duty-cycle distortion at the receiver.
Estimated: When routing the four differential outputs, use 100 ohm differential impedance with 8 mil-to-10 mil trace width on standard FR-4 stackups; pair each output with its complementary trace within 5 mil spacing. Place the input reference traces on a different layer than the outputs to minimize reference jitter pickup. For 56G PAM4 use cases, route the output traces on the top layer over a continuous ground plane to suppress mode conversion.
Do not apply power to the SI5394A-A-GM before the ClockBuilder Pro-generated NVM image is loaded, because the device defaults to a safe low-frequency output until the host MCU configures it. Verify that the I2C/SPI pull-up resistors match the bus speed (typically 4.7 kohm for 100 kHz, 2.2 kohm for 400 kHz). Also be aware that downstream SerDes PHYs may need a fixed-frequency reference at power-up; if so, program the device's NVM image with a known good frequency plan before deployment.
Información de cumplimiento
RoHS compliant per DigiKey and Mouser listings; AEC-Q100 not applicable as this is a general-purpose industrial/telecom timing part
